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Section 5 Interrupt Controller
Interrupt Acceptance Control and 3-Level Control: In interrupt control modes 0 and 1,
interrupt acceptance control and 3-level mask control is performed by means of the I and UI bits in
CCR and ICR (control level).
Table 5.5 shows the interrupts selected in each interrupt control mode.
Table 5.5
Interrupts Selected in Each Interrupt Control Mode
Interrupt Control Mode I
0
1
[Legend]
Don't care
*
Default Priority Determination: The priority is determined for the selected interrupt, and a
vector number is generated.
If the same value is set for ICR, acceptance of multiple interrupts is enabled, and so only the
interrupt source with the highest priority according to the preset default priorities is selected and
has a vector number generated.
Interrupt sources with a lower priority than the accepted interrupt source are held pending.
Table 5.6 shows operations and control signal functions in each interrupt control mode.
Rev. 1.00 Mar. 12, 2008 Page 92 of 1178
REJ09B0403-0100
Interrupt Mask Bits
UI
0
*
1
*
0
*
1
0
1
Selected Interrupts
All interrupts (interrupt control level 1 has
priority)
NMI and address break interrupts
All interrupts (interrupt control level 1 has
priority)
NMI, address break, and interrupt control level 1
interrupts
NMI and address break interrupts
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