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Bit
Bit Name
1
EP2DMAE
Initial
Value
R/W
Description
0
R/W
Endpoint 2 DTC Transfer Enable
When this bit is set, DTC transfer is enabled from
memory to the endpoint 2 transmit FIFO buffer. If
there is at least one byte of space in the FIFO buffer,
the DTC start interrupt signal (USBINTN1) is asserted.
In DTC transfer, when 64 bytes are written to the
FIFO buffer the EP2 packet enable bit is set
automatically, allowing 64 bytes of data to be
transferred, and if there is still space in the other of
the two FIFOs, the DTC start interrupt signal
(USBINTN1) is asserted again. However, if the size of
the data packet to be transmitted is less than 64
bytes, the EP2 packet enable bit is not set
automatically, and so should be set by the CPU on a
DTC transfer end interrupt.
As EP2-related interrupt requests to the CPU are not
automatically masked, interrupt requests should be
masked as necessary in the interrupt enable register.
•
1. Set the number of transfers in the DTC.
2. Set the DTC to be activated by USBINTN1.
3. Write 1 to this bit.
4. Activate the DTC.
5. DTC transfer is performed.
6. DTC transfer end interrupt is generated.
7. Write 0 to the EP1DMAE bit in DMA.
8. Write 0 to the EP1FULL bit in IFR0.
See section 22.8.3, DTC Transfer for Endpoint 2.
Section 22 USB Function Module (USB)
Operating procedure
Rev. 1.00 Mar. 12, 2008 Page 851 of 1178
REJ09B0403-0100
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