Renesas H8S Family Hardware Manual page 199

φ
CS256
IOS
WAIT
AH
RD
HWR
LWR
AD15 to AD8
AD7 to AD0
Figure 6.29 Example of Wait State Insertion Timing
Read Cycle
Data
T T T T T
3 4 DSW DOW DOW
Section 6 Bus Controller (BSC)
Write Cycle
T T T T
5 3 4 DSW
Data
Data
Rev. 1.00 Mar. 12, 2008 Page 151 of 1178
Data
T T T
DOW DOW 5
Data
Data
REJ09B0403-0100