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Bit
Bit Name
1
HBTWIE
0
HBTRIE
Note:
X Don't care.
19.3.28 BT Control Status Register 1 (BTCSR1)
BTCSR1 is one of the registers used to implement the BT mode. The BTCSR1 register contains
the bits used to enable or disable interrupts to the slave (this LSI). The IBFI3 interrupt is enabled
by setting the IBFIE3 bit in HICR2 to 1.
Bit
Bit Name
7
RSTRENBL 0
6
HRSTIE
R/W
Initial
Value
Slave Host Description
0
R/W
0
R/W
R/W
Initial
Value
Slave Host
R/W
0
R/W
BTDTR Host Write Start Interrupt Enable
Enables or disables the HBTWI interrupt which is an
IBFI3 interrupt source to the slave.
0: BTDTR host write start interrupt is disabled.
1: BTDTR host write start interrupt is enabled.
BTDTR Host Read End Interrupt Enable
Enables or disables the HBTRI interrupt which is an
IBFI3 interrupt source to the slave.
0: BTDTR host read end interrupt is disabled.
1: BTDTR host read end interrupt is enabled.
Description
Slave Reset Read Enable
The host reads 0 from the BMC_HWRST bit in
BTIMSR. When this bit is set to 1, the host can read
1 from the BMC_HWRST bit.
0: Host always reads 0 from BMC_HWRST
1: Host can reads 0 from BMC_HWRST
BT Reset Interrupt Enable
Enables or disables the HRSTI interrupt which is an
IBFI3 interrupt source to the slave.
0: BT reset interrupt is disabled.
1: BT reset interrupt is enabled.
Rev. 1.00 Mar. 12, 2008 Page 725 of 1178
Section 19 LPC Interface (LPC)
REJ09B0403-0100
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