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Section 17 Synchronous Serial Communication Unit (SSU)
Bit
Bit Name
2
TDRE
1
RDRF
0
CE
Rev. 1.00 Mar. 12, 2008 Page 560 of 1178
REJ09B0403-0100
Initial
R/W
Value
1
R/W
0
R/W
0
R/W
Description
Transmit Data Empty
Indicates whether or not SSTDR contains transmit data.
[Setting conditions]
•
When the TE bit in SSER is 0
•
When data is transferred from SSTDR to SSTRSR
and SSTDR is ready to be written to.
[Clearing conditions]
•
When writing 0 after reading TDRE = 1
•
When writing data to SSTDR with TE = 1
Receive Data Register Full
Indicates whether or not SSRDR contains receive data.
[Setting condition]
•
When receive data is transferred from SSTRSR to
SSRDR after successful serial data reception
[Clearing conditions]
•
When writing 0 after reading RDRF = 1
•
When reading receive data from SSRDR
Conflict/Incomplete Error
Indicates that a conflict error has occurred
when 0 is externally input to the SCS pin with SSUMS
= 0 (SSU mode) and MSS = 1 (master mode).
If the SCS pin level changes to 1 with SSUMS = 0 (SSU
mode) and MSS = 0 (slave mode), an incomplete error
occurs because it is determined that a master device
has terminated the transfer. Data reception does not
continue while the CE bit is set to 1. Serial transmission
also does not continue. Reset the SSU internal
sequencer by setting the SRES bit in SSCRL to 1
before resuming transfer after incomplete error.
[Setting condition]
When a low level is input to the SCS pin in master
•
mode (the MSS bit in SSCRH is set to 1)
When the SCS pin is changed to 1 during transfer in
•
slave mode (the MSS bit in SSCRH is cleared to 0)
[Clearing condition]
•
When writing 0 after reading CE = 1
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