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(2)
Port 5 Data Register (P5DR)
P5DR stores output data for the port 5 pins.
Bit
Bit Name
7
P57DR
6
P56DR
5
P55DR
4
P54DR
3
P53DR
2
P52DR
1
P51DR
0
P50DR
Note:
* The initial value is determined in accordance with the pin state of P56.
(3)
Pin Functions
(a)
Normal Extended Mode and Address-Data Multiplex Extended Mode
Port pin 57 is automatically set to function as a bus control output pin. The functions of port pins
56 to 50 are the same as those in single-chip mode.
(b)
Single-Chip Mode
Port 5 pins can operate as the SCIF, SCI_1, and SSU input/output, noise canceler input, or general
I/O port pins. The relationship between register setting values and pin functions are as follows.
• P57
The pin function is switched as shown below according to the P57DDR bit.
P57DDR
Pin function
Initial Value
R/W
0
R/W
Undefined*
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
P57 input pin
Description
P5DR stores output data for the port 5 pins that are
used as the general output port.
If this register is read, the P5DR values are read for
the bits with the corresponding P5DDR bits set to 1.
For the bits with the corresponding P5DDR bits
cleared to 0, the pin states are read.
Rev. 1.00 Mar. 12, 2008 Page 215 of 1178
Section 8 I/O Ports
1
P57 output pin
REJ09B0403-0100
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