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Section 6 Bus Controller (BSC)
CS256
AD15 to AD8
AD7 to AD0
Figure 6.22 Bus Timing for 16-Bit, 2-State Access Space (4) (Odd Byte Access)
Rev. 1.00 Mar. 12, 2008 Page 144 of 1178
REJ09B0403-0100
Read Cycle
Address
T
T
1
2
φ
CK2S
IOS
AH
RD
HWR
LWR
Address
Address
Data
Address
T
T
T
3
4
1
Address
Data
Address
Write Cycle
Data
T
T
T
2
3
4
Data
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