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Section 6 Bus Controller (BSC)
• Multiplex bus interface
Address
256-Kbyte
2 states*
extended area
IOS extended area 2 states*
Note:
* A wait cycle is inserted by the setting of the WC22 bit.
• Basic bus interface
2-state access or 3-state access can be selected for each area.
Program wait states can be inserted for each area.
• Burst ROM interface
In normal extended mode
A burst ROM interface can be set for basic extended areas.
1-state access or 2-state access can be selected for burst access.
• Idle cycle insertion
In normal extended mode
An idle cycle can be inserted for external write cycles immediately after external read cycles.
• Bus arbitration function
Includes a bus arbiter that arbitrates bus mastership between the CPU, DTC, and E-DMAC.
Rev. 1.00 Mar. 12, 2008 Page 106 of 1178
REJ09B0403-0100
No Wait Inserted
Data
2 states
2 states
Wait Inserted
Address
Data
2 states*
(3 + wait) states
2 states*
(3 + wait) states
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