Interrupt Exception Handling Vector Table - Renesas H8S Family Hardware Manual

Section 5 Interrupt Controller

Interrupt Exception Handling Vector Table

Table 5.3 lists interrupt exception handling sources, vector addresses, and interrupt priorities. For

default priorities, the lower the vector number, the higher the priority. Modules set at the same

priority will conform to their default priorities. Priorities within a module are fixed.

An interrupt control level can be specified for a module to which an ICR bit is assigned. Interrupt

requests from modules that are set to interrupt control level 1 (priority) by the ICR bit setting are

given priority and processed before interrupt requests from modules that are set to interrupt

control level 0 (no priority).

Interrupt Sources, Vector Addresses, and Interrupt Priorities

External pin

SWDTEND (Software activation

data transfer end)

WOVI0 (Interval timer)

WOVI1 (Interval timer)

Address break

A/D converter ADI (A/D conversion end)

CMIAX (Compare match A)

CMIBX (Compare match B)

OVIX (Overflow)

OCIA (Output compare A)

OCIB (Output compare B)

FOVI (Overflow)

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REJ09B0403-0100

Vector Address

Number Advanced Mode