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Table 22.4 Relationship between TRNTREG0 Setting and Pin Output
Pin Input
VBUS
PTSTE
0
X
1
0
1
1
1
1
1
1
1
1
[Legend]
X:
Don't care.
:
Cannot be controlled. Indicates state in normal operation according to the USB operation
and port settings.
22.3.27 Transceiver Test Register 1 (TRNTREG1)
TRNTREG1 is a test register that can monitor the built-in transceiver input signal.
Setting bits PTSTE and txenl in TRNTREG0 to 1 enables monitoring the built-in transceiver input
signal. Table 22.5 shows the relationship between pin input and TRNTREG1 monitoring value.
Bit
Bit Name
7 to 3
2
xver_data
1
dpls
0
dmns
Note:
* Determined by the state of pins, VBUS, USD+, and USD-
Register Setting
txenl
txse0
X
X
X
X
0
0
0
0
0
1
1
X
Initial
Value
R/W
Description
Reserved
All 0
R
These bits are always read as 0. The initial value
should not be changed.
*
R
Built-In Transceiver Input Signal Monitor
*
R
xver_data: Monitors the differential input level
*
R
dpls:
dmns:
Section 22 USB Function Module (USB)
txdata
USD+
X
Hi-Z
X
0
0
1
1
x
0
X
Hi-Z
(xver_data) signal of the built-in transceiver.
Monitors the USD+ (dpls) signal of the built-
in transceiver.
Monitors the USD- (dmns) signal of the built-
in transceiver.
Rev. 1.00 Mar. 12, 2008 Page 861 of 1178
Pin Output
USD-
Hi-Z
1
0
0
Hi-Z
REJ09B0403-0100
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