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Initial
Bit
Bit Name
Value
2
IBFIE2
0
1
IBFIE1
0
0
ERRIE
0
Note:
* Only 0 can be written to bits 6 to 4, to clear the flag.
• HICR3
Bit
Bit Name Initial Value Slave Host Description
7
LFRAME Undefined
6
CLKRUN Undefined
5
SERIRQ
Undefined
4
LRESET
Undefined
3
LPCPD
Undefined
2
PME
Undefined
1
LSMI
Undefined
0
LSCI
Undefined
R/W
Slave Host Description
R/W
IDR2 Receive Complete interrupt Enable
Enables or disables IBFI2 interrupt to the slave (this
LSI).
0: Input data register (IDR2) receive complete
interrupt requests disabled
1: Input data register (IDR2) receive complete
interrupt requests enabled
R/W
IDR1 Receive Complete interrupt Enable
Enables or disables IBFI1 interrupt to the slave (this
LSI).
0: Input data register (IDR1) receive complete
interrupt requests disabled
1: Input data register (IDR1) receive complete
interrupt requests enabled
R/W
Error Interrupt Enable
Enables or disables ERRI interrupt to the slave (this
LSI).
0: Error interrupt requests disabled
1: Error interrupt requests enabled
R/W
LFRAME Pin Monitor
R
CLKRUN Pin Monitor
R
R
SERIRQ Pin Monitor
LRESET Pin Monitor
R
LPCPD Pin Monitor
R
PME Pin Monitor
R
LSMI Pin Monitor
R
R
LSCI Pin Monitor
Section 19 LPC Interface (LPC)
Rev. 1.00 Mar. 12, 2008 Page 681 of 1178
REJ09B0403-0100
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