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Section 6 Bus Controller (BSC)
Table 6.3
Bit Settings and Bus Specifications of Basic Bus Interface
BRSTRM
CS256E
0
0
1
1
0
1
Note:
* In the burst ROM interface, the bus width is specified by the ABW bit in WSCR, the
number of full access states (wait can be inserted) is specified by the AST bit in WSCR,
and the number of access cycles in burst access is specified regardless of the AST bit
setting.
Table 6.4
Bus Specifications for Basic Extended Area/Basic Bus Interface
ABW
AST
WMS1
0
0
X
1
0
Other than
WMS1 = 0 and
WMS0 = 1
1
0
X
1
0
Other than
WMS1 = 0 and
WMS0 = 1
[Legend]
X:
Don't care
Rev. 1.00 Mar. 12, 2008 Page 118 of 1178
REJ09B0403-0100
Basic Extended Area
Basic extended area
ABW, AST,
WMS1, WMS0,
WC1, WC0
Burst ROM interface*
ABW, AST, WMS0, WC1, WC0,
BRSTS1, BRSTS0
WMS0
WC1
WC0
X
X
X
1
X
X
0
0
1
1
0
1
X
X
X
1
X
X
0
0
1
1
0
1
Areas
256-Kbyte Extended Area
Used as basic extended area
ABW256, AST256, WMS10,
WC11, WC10
Used as burst ROM interface
ABW256, AST256, WMS10,
WC11, WC10
Bus Specifications
Number of
Access
Bus Width
States
16
2
16
3
3
8
2
8
3
3
Number of
Program
Wait
States
0
0
0
1
2
3
0
0
0
1
2
3
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