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22.3.3
Interrupt Flag Register 2 (IFR2)
IFR2, together with interrupt flag registers 0 and 1 (IFR0 and IFR1), indicates interrupt status
information required by the application. When an interrupt source is generated, the corresponding
bit is set to 1. And then this bit, in combination with interrupt enable register 2 (IER2), generates
an interrupt request to the CPU. To clear, write 0 to the bit to be cleared and 1 to the other bits.
Bit
Bit Name
7, 6
5
SURSS
4
SURSF
3
CFDN
2
SOF
1
SETC
0
SETI
Initial
Value
R/W
Description
All 0
R
Reserved
These bits are always read as 0. The initial value
should not be changed.
0
R
Suspend/Resume Status
This is a status bit that describes bus state.
0: Normal state
1: Suspended state
This bit is a status bit and generates no interrupt
request.
0
R/W
Suspend/Resume Detection
This bit is set to 1 when the state changed from normal
to suspended state or vice versa. The corresponding
interrupt output is RESUME, USBINTN2, and
USBINTN3.
0
R/W
End Point Information Load End
This bit is set to 1 when writing data in the endpoint
information register to the EPIR register ends (load
end). This module starts the USB operation after the
endpoint information is completely set.
0
R
SOF Interrupt Detection
This bit is set to 1 when an SOF interrupt is detected.
0
R/W
Set_Configuration Command Detection
When the Set_Configuration command is detected, this
bit is set to 1.
0
R/W
Set_Interface Command Detection
When the Set_Interface command is detected, this bit
is set to 1.
Section 22 USB Function Module (USB)
Rev. 1.00 Mar. 12, 2008 Page 839 of 1178
REJ09B0403-0100
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