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Bit
Bit Name
25
RABT
24
RFCOF
23
ADE
22
ECI
Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Initial
value
R/W
Description
0
R/W
Receive Abort Detection
Indicates that the EtherC aborts receiving a frame
because of failures during receiving the frame.
0: Frame reception has not been aborted or no
1: Frame receive has been aborted
0
R/W
Receive Frame Counter Overflow
Indicates that the receive FIFO frame counter has
overflowed.
0: Receive frame counter has not overflowed
1: Receive frame counter overflows
0
R/W
Address Error
Indicates that the memory address that the E-DMAC
tried to transfer is found illegal.
0: Illegal memory address not detected (normal
1: Illegal memory address detected
Note: When an address error is detected, the
0
R
EtherC Status Register Interrupt Source
This bit is a read-only bit. When the source of an
ECSR interrupt in the EtherC is cleared, this bit is
also cleared.
0: EtherC status interrupt source has not been
1: EtherC status interrupt source has been detected
receive directive
operation)
E-DMAC halts transmitting/receiving. To
resume the operation, set the E-DMAC again
after software reset by means of the SWR bit in
EDMR.
detected
Rev. 1.00 Mar. 12, 2008 Page 799 of 1178
REJ09B0403-0100
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