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Table 7.1
Correspondence between Interrupt Sources and DTCER
Bit
Bit Name
DTCERA
7
DTCEn7
(16)IRQ0
6
DTCEn6
(17)IRQ1
5
DTCEn5
(18)IRQ2
4
DTCEn4
(19)IRQ3
3
DTCEn3
(28)ADI
2
DTCEn2
1
DTCEn1
0
DTCEn0
[Legend]
n:
A to F
( ):
Vector number
:
Reserved. The write value should always be 0.
Only in the H8S/2472
*:
7.2.8
DTC Vector Register (DTVECR)
DTVECR enables or disables DTC activation by software, and sets a vector number for the
software activation interrupt.
Bit
Bit Name
7
SWDTE
DTCERB
(76)IICI2
(94)IICI0
Initial
Value
R/W
Description
0
R/W
DTC Software Activation Enable
Setting this bit to 1 activates DTC. Only 1 can be written to
this bit.
[Clearing conditions]
•
•
This bit will not be cleared when the DISEL bit is 1 and
data transfer has ended or when the specified number of
transfers has ended.
Section 7 Data Transfer Controller (DTC)
Register
DTCERC
DTCERD
(86)TXI1
(89)RXIS
(90)TXIS
(29)EVENTI (78)IICI3
(98)IICI1
(81)RXI3
(82)TXI3
(85)RXI1
When the DISEL bit is 0 and the specified number of
transfers have not ended
When 0 is written to the DISEL bit after a software-
activated data transfer end interrupt (SWDTEND)
request has been sent to the CPU.
Rev. 1.00 Mar. 12, 2008 Page 165 of 1178
DTCERE
DTCERF*
(115)USBINT0
(118)USBINT1
(104)ERR1
(105)IBFI1
(106)IBFI2
(107)IBFI3
REJ09B0403-0100
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