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Section 23 A/D Converter
23.4.3
Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when the A/D conversion start delay time (t
) has passed after the ADST bit in ADCSR is
D
set to 1, then starts A/D conversion. Figure 23.4 shows the A/D conversion timing. Tables 23.3
and 23.4 show the A/D conversion time.
As indicated in figure 23.4, the A/D conversion time (t
) includes t
and the input sampling time
CONV
D
(t
). The length of t
varies depending on the timing of the write access to ADCSR. The total
SPL
D
conversion time therefore varies within the ranges indicated in table 23.3.
In scan mode, the values given in table 23.3 apply to the first conversion time. The values given in
table 23.4 apply to the second and subsequent conversions. In either case, bits CKS1 and CKS0 in
ADCR should be set so that the conversion time is within the ranges indicated by the A/D
conversion characteristics.
Rev. 1.00 Mar. 12, 2008 Page 905 of 1178
REJ09B0403-0100
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