Renesas H8S Family Hardware Manual page 634

2
Section 18 I C Bus Interface (IIC)
 Pins SCL0 to SCL5 and SDA0 to SDA5 (normally NMOS push-pull outputs) function as
NMOS open-drain outputs when the bus drive function is selected.
Figure 18.1 shows a block diagram of the I
pin connections to external circuits. Since I
normal port pins, they have different specifications for permissible applied voltages. For details,
see section 31, Electrical Characteristics.
φ
SCL
canceler
SDA
canceler
[Legend]
ICCR: I 2 C bus control register
ICMR: I 2 C bus mode register
ICSR: I 2 C bus status register
2
ICDR: I C bus data register
2
ICXR: I C bus extended control register
SAR: Slave address register
SARX: Slave address register X
PS: Prescaler
Rev. 1.00 Mar. 12, 2008 Page 586 of 1178
REJ09B0403-0100
PS
Clock
control
Noise
Bus state
decision
circuit
Arbitration
decision
circuit
Output data
control
circuit
Noise
Figure 18.1 Block Diagram of I
2
C bus interface. Figure 18.2 shows an example of I/O
2
C bus interface I/O pins are different in structure from
Address comparator
SAR, SARX
2
C Bus Interface
ICXR
ICCR
ICMR
ICSR
ICDRT
ICDRS
ICDRR
Interrupt
Interrupt
generator
generator