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Master transmit mode
SCL
(master output)
9
SDA
A
(slave output)
SDA
(master output)
IRIC
IRTR
ICDR
User processing
[1] TRS cleared to 0
IRIC clear to 0
Figure 18.15 Master Receive Mode Operation Timing Example
SCL
8
(master output)
SDA
Bit 0
(slave output)
Data 2
[3]
SDA
A
(master output)
IRIC
IRTR
[4] IRTR=0
ICDR
Data 1
User processing
[6] IRIC clear
(to end wait
insertion)
Figure 18.16 Stop Condition Issuance Timing Example in Master Receive Mode
Master receive mode
1
2
3
4
Bit 7
Bit 6
Bit 5
Bit 4
Data 1
[2] ICDR read
(dummy read)
(MLS = ACKB = 0, WAIT = 1)
[8] Wait for one clock pulse
9
1
2
3
Bit 7
Bit 6
Bit 5
Bit 4
Data 3
[3]
[4] IRTR=1
Data 2
[11] IRIC clear
[10] ICDR read (Data 2)
[9] Set TRS=1
[7] Set ACKB=1
(MLS = ACKB = 0, WAIT = 1)
5
6
7
8
Bit 3
Bit 2
Bit 1
Bit 0
[3]
[4]IRTR=0
[6] IRIC clear
(to end wait insertion)
4
5
6
7
8
Bit 3
Bit 2
Bit 1
Bit 0
[12]
[13] IRTR=0
Rev. 1.00 Mar. 12, 2008 Page 631 of 1178
2
Section 18 I
C Bus Interface (IIC)
9
1
2
Bit 7
Bit 6
Bit 5
Data 2
[3]
A
[4] IRTR=1
Data 1
[5] ICDR read
[6] IRIC clear
(Data 1)
Stop condition generation
9
[12]
A
[13] IRTR=1
Data 3
[15] WAIT cleared to 0,
IRIC clear
[17] Stop condition issuance
[14] IRIC clear
(to end wait
[16] ICDR read
insertion)
(Data 3)
REJ09B0403-0100
3
4
5
Bit 4
Bit 3
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