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19.3.1
Host Interface Control Registers 0 and 1 (HICR0 and HICR1)
HICR0 and HICR1 contain control bits that enable or disable LPC interface functions, control bits
that determine pin output and the internal state of the LPC interface, and status flags that monitor
the internal state of the LPC interface.
• HICR0
Bit
Bit Name
7
LPC3E
6
LPC2E
5
LPC1E
R/W
Initial
Value
Slave Host Description
0
R/W
0
R/W
0
R/W
LPC Enable 3 to 1
Enable or disable the LPC interface function. When
the LPC interface is enabled (one of the three bits is
set to 1), processing for data transfer between the
slave (this LSI) and the host is performed using pins
LAD3 to LAD0, LFRAME, LRESET, LCLK, SERIRQ,
CLKRUN, and LPCPD.
•
LPC3E
0: LPC channel 3 operation is disabled
No address (LADR3) matches for IDR3, ODR3,
STR3, TWR0 to TWR15, SMIC, KCS, or BT
1: LPC channel 3 operation is enabled
•
LPC2E
0: LPC channel 2 operation is disabled
No address (LADR2) matches for IDR2, ODR2, or
STR2
1: LPC channel 2 operation is enabled
•
LPC1E
0: LPC channel 1 operation is disabled
No address (LADR1) matches for IDR1, ODR1, or
STR1
1: LPC channel 1 operation is enabled
Rev. 1.00 Mar. 12, 2008 Page 671 of 1178
Section 19 LPC Interface (LPC)
REJ09B0403-0100
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