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Noise Canceler Cycle Setting Register (NCCS)
NCCS controls the sampling cycle of the noise cancelers.
Bit
Bit Name Initial Value R/W Description
7 to 3
Undefined
2
NCCK2
0
1
NCCK1
0
0
NCCK0
0
Sampling clock selection
∆t
Pin input
Latch
Sampling clock
R/W Reserved
Undefined value is read from these bits.
R/W
These bits set the sampling cycle of the noise cancelers.
•
R/W
R/W
φ/2, φ/32, φ/512, φ/8192,
φ/32768, φ/65536,
φ/131072, φ/262144
Latch
Latch
∆t
Figure 8.1 Noise Canceler Circuit
When φ = 34 MHz
000: 0.06 µs
φ/2
001: 0.94 µs
φ/32
010: 15.1 µs
φ/512
011: 240.9 µs φ/8192
Rev. 1.00 Mar. 12, 2008 Page 203 of 1178
Section 8 I/O Ports
100: 963.8 µs φ/32768
φ/65536
101: 1.9 ms
φ/131072
110: 3.9 ms
φ/262144
111: 7.7 ms
Match
detection
circuit
REJ09B0403-0100
Port data
register
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