Operation - Renesas H8S Family Hardware Manual

19.4

LPC interface Activation

The LPC interface is activated by setting any one of bits LPC3E to LPC1E in HICR0 and bit

SICIE bit in HICR5 to 1. When the LPC interface is activated, the related I/O port pins (PE7 to

PE0, PD5 and PD4) function as dedicated LPC interface input/output pins. In addition, setting the

FGA20E, PMEE, LSMIE, and LSCIE bits to 1 adds the related I/O port pins (PD3 to PD0) to the

LPC interface's input/output pins.

Use the following procedure to activate the LPC interface after a reset release.

1. Read the signal line status and confirm that the LPC module can be connected. Also check that

the LPC module is initialized internally.

2. When using channels 1 and 2, set LADR1 and LADR2 to determine the I/O address.

3. When using channel 3, set LADR3 to determine the I/O address and whether bidirectional data

registers are to be used.

4. When using the SCIF module, set SCIFAR to determine the I/O address.

5. Set the enable bit (LPC3E to LPC1E) for the channel to be used. Also set SCIFE if the SCIF is

6. Set the enable bits (FGA20E, PMEE, LSMIE, and LSCIE) for the additional functions to be

7. Set the selection bits for other functions (SDWNE, IEDIR).

8. As a precaution, clear the interrupt flags (LRST, SDWN, ABRT, OBF, and OBEI). Read IDR

or TWR15 to clear IBF.

9. Set receive complete interrupt enable bits (IBFIE3 to IBFIE1, and ERRIE) as necessary.

LPC I/O Cycles

There are 12 types of LPC transfer cycle: LPC memory read, LPC memory write, I/O read, I/O

write, DMA read, DMA write, bus master memory read, bus master memory write, bus master I/O

read, bus master I/O write, FW memory read, and FW memory write. Of these, the LPC of this

LSI supports I/O read and I/O write.

Section 19 LPC Interface (LPC)

Rev. 1.00 Mar. 12, 2008 Page 733 of 1178

REJ09B0403-0100