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21.2.12 Receiving method Control Register (RMCR)
RMCR is a 32-bit readable/writable register that specifies the control method for the RR bit in
EDRRR when a frame is received. This register must be set during the receiving-halt state.
Bit
Bit Name
31 to 1
0
RNC
Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Initial
value
R/W
Description
All 0
R
Reserved
These bits are always read as 0. The initial value
should not be changed.
0
R/W
Receive Enable Control
0: When reception of one frame is completed, the E-
1: When reception of one frame is completed, the E-
DMAC writes the receive status into the descriptor
and clears the RR bit in EDRRR
DMAC writes the receive status into the descriptor,
reads the next descriptor, and prepares to receive
the next frame
Rev. 1.00 Mar. 12, 2008 Page 811 of 1178
REJ09B0403-0100
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