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Section 23 A/D Converter
4. The ADST bit is not automatically cleared to 0 and steps 2 to 3 are repeated as long as the
ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops and the
A/D converter enters the idle state. After that, when the ADST bit is set to 1, the operation
starts from the first channel again.
ADST
ADF
State of channel 0
(AN0)
State of channel 1
(AN1)
State of channel 2
(AN2)
State of channel 3
(AN3)
ADDRA
ADDRB
ADDRC
ADDRD
Notes :
1.
indicates execution of a software instruction.
2. The data being converted is ignored
(When Channels AN0 to AN3 are Selected in Scan Mode)
Rev. 1.00 Mar. 12, 2008 Page 904 of 1178
REJ09B0403-0100
Continuous execution of A/D conversion
1
Set*
Idle
A/D conversion 1
Idle
A/D conversion 2
Idle
Transfer
Figure 23.3 Example of A/D Converter Operation
A/D conversion time
Idle
A/D conversion 4
Idle
A/D conversion 3
Idle
Result of A/D conversion 1
Result of A/D conversion 2
1
Clear*
Idle
2
*
Idle
A/D conversion 5
Idle
Result of A/D conversion 4
Result of A/D conversion 3
1
Clear*
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