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• PB3/EVENT11/DB3/RM_RXD1, PB2/EVENT10/DB2/RM_RXD0,
PB1/EVENT9/DB1/RM_TXD1, PB0/EVENT8/DB0/RM_TXD0
The pin function is switched as shown below according to the combination of the module stop
state in the EtherC and E-DMAC and the PBnDDR bit.
EtherC,
E-DMAC
PBnDDR
Event
Disabled
counter
PBnNCE
0
Pin
PBn
function
input
[Legend]
n = 3 to 0, m = 11 to 8, X: Don't care.
Either of them is stopped
0
Enabled
1
X
DBn
EVENTm input
input
1
X
X
PBn output pin
Rev. 1.00 Mar. 12, 2008 Page 335 of 1178
Section 8 I/O Ports
Both of them are
stopped
X
X
X
RM_xxxx
EtherC I/O pin
REJ09B0403-0100
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