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Bit
Bit Name
4
OEM3
3
OEM2
2
OEM1
1
B2H_IRQ
0
B2H_IRQ_EN 0
Notes: 1. Only 1 can be written to set this flag.
2. Only 0 can be written to clear this flag.
3. Only 1 can be written to clear this flag.
4.
Only 0 can be written to set this flag.
R/W
Initial
Value Slave
Host
0
R/W
R/(W)*
0
R/W
R/(W)*
0
R/W
R/(W)*
1
0
R/(W)*
R/(W)*
R
R/W
Description
4
User defined bit
4
These bits are defined by the user and are valid
only when set to 1 by a 0 written from the host.
4
0: [Clearing condition]
When the slave writes a 0, after a 1 has been
read from OEM.
1: [Setting condition]
When the slave writes a 1, after a 0 has been
read from OEM, or when the host writes a 0.
3
BMC to HOST interrupt
Informs the host that an interrupt has been
requested when the BEVT_ATN or B2H_ATN bit
has been set. The SERIRQ is not issued. To
generate the SERIRQ, it should be issued by the
program.
0: B2H_IRQ interrupt is not requested
[Clearing condition]
When the host writes a 1.
1: B2H_IRQ interrupt is requested
[Setting condition]
When the slave writes a 1, after a 0 has been read
from B2H_IRQ
BMC to HOST interrupt enable
Enables or disables the B2H_IRQ interrupt which
is an interrupt source from the slave to the host.
0: B2H_IRQ interrupt is disabled
[Clearing condition]
When a 0 is written by the host.
1: B2H_IRQ interrupt is enabled
[Setting condition]
When a 1 is written by the host.
Rev. 1.00 Mar. 12, 2008 Page 731 of 1178
Section 19 LPC Interface (LPC)
REJ09B0403-0100
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