User Manuals: Renesas R4F2462 Microcontroller IC

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Renesas R4F2462 Hardware Manual (1230 pages)

Brand: Renesas | Category: Computer Hardware | Size: 8 MB

General Precautions on Handling of Product
4
Preface
6
Table of Contents
9
Table of Contents
10
Table of Contents
11
Table of Contents
12
Table of Contents
13
Table of Contents
14
Table of Contents
15
Table of Contents
16
Table of Contents
17
Table of Contents
18
Table of Contents
19
Table of Contents
20
Table of Contents
21
Table of Contents
22
Table of Contents
23
Table of Contents
24
Table of Contents
25
Table of Contents
26
Table of Contents
27
Overview
49
Block Diagram
51
Pin Description
52
Pin Assignments
52
53
Overview
53
Pin Assignment in each Operating Mode
54
Manual
58
Pin Functions
61
Features
71
Differences between H8S/2600 CPU and H8S/2000 CPU
72
Differences from H8/300 CPU
73
CPU Operating Modes
74
Advanced Mode
76
Address Space
78
Registers
79
General Registers
80
Program Counter (PC)
81
Condition-Code Register (CCR)
82
Multiply-Accumulate Register (MAC)
83
Data Formats
84
Memory Data Formats
86
Instruction Set
87
Table of Instructions Classified by Function
88
Basic Instruction Formats
98
Addressing Modes and Effective Address Calculation
99
Register Indirect with Displacement@(D:16, Ern) or @(D:32, Ern)
100
Immediate#XX:8, #XX:16, or #XX:32
101
Memory Indirect@@Aa:8
102
Effective Address Calculation
103
Processing States
105
Usage Note
107
Section 3 MCU Operating Modes
109
Register Descriptions
110
System Control Register (SYSCR)
111
Serial Timer Control Register (STCR)
112
Operating Mode Descriptions
114
Address Map
115
Section 4 Exception Handling
117
Exception Sources and Exception Vector Table
118
Reset
120
Interrupts after Reset
121
Interrupt Exception Handling
122
Stack Status after Exception Handling
123
124
Usage Note
124
Section 5 Interrupt Controller
125
Input/Output Pins
126
127
Register Descriptions
127
Address Break Control Register (ABRKCR)
128
Break Address Registers a to C (BARA to BARC)
129
IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH, ISCRL)
130
IRQ Enable Registers (IER16, IER)
132
IRQ Status Registers (ISR16, ISR)
133
Interrupt Sources
134
Internal Interrupts
135
Interrupt Exception Handling Vector Table
136
Interrupt Control Modes and Interrupt Operation
139
Interrupt Control Mode 0
141
Interrupt Control Mode 1
143
Interrupt Exception Handling Sequence
146
Interrupt Response Times
147
DTC Activation by Interrupt
148
Usage Notes
150
Instructions that Disable Interrupts
151
153
Features
153
156
Input/Output Pins
156
157
Register Descriptions
157
Bus Control Register 2 (BCR2)
159
Wait State Control Register (WSCR)
160
Wait State Control Register 2 (WSCR2)
162
System Control Register 2 (SYSCR2)
163
Bus Control
164
171
Advanced Mode
171
I/O Select Signals
172
Bus Interface
173
Valid Strobes
175
Valid Strobes (in Glueless Extension)
176
Basic Operation Timing in Normal Extended Mode
177
Basic Operation Timing in Address-Data Multiplex Extended Mode
188
Wait Control
196
Burst ROM Interface
200
201
Wait Control
201
Idle Cycle
202
Bus Arbitration
203
Bus Mastership Transfer Timing
204
207
Features
207
209
Register Descriptions
209
DTC Mode Register a (MRA)
210
DTC Mode Register B (MRB)
211
DTC Transfer Count Register a (CRA)
212
DTC Vector Register (DTVECR)
213
Keyboard Comparator Control Register (KBCOMP)
214
Event Counter Control Register (ECCR)
215
Event Counter Status Register (ECS)
216
DTC Event Counter
217
Event Counter Handling Priority
218
219
Usage Notes
219
Location of Register Information and DTC Vector Table
221
Operation
223
Normal Mode
224
Repeat Mode
225
Block Transfer Mode
226
Chain Transfer
227
228
Interrupt Sources
228
Number of DTC Execution States
230
Procedures for Using DTC
231
Examples of Use of the DTC
232
Software Activation
233
234
Usage Notes
234
I/O Ports for the H8S/2472 Group
235
Port 1
240
Port 2
243
Port 3
248
Port 4
254
Port 5
262
Port 6
267
Port 7
273
Port 8
277
Port 9
282
Port a
286
Port B
294
Port C
300
Port D
305
Port E
310
Port F
314
I/O Ports for the H8S/2462 Group
318
323
Port 1
323
326
Port 2
326
331
Port 3
331
337
Port 4
337
345
Port 5
345
350
Port 6
350
357
Port 7
357
361
Port 8
361
366
Port 9
366
370
Port a
370
378
Port B
378
384
Port C
384
389
Port D
389
394
Port E
394
399
Port F
399
Change of Peripheral Function Pins
402
Port Control Register 0 (PTCNT0)
404
Section 9 14-Bit PWM Timer (PWMX)
405
406
Input/Output Pins
406
PWMX (D/A) Counter (DACNT)
407
PWMX (D/A) Data Registers a and B (DADRA and DADRB)
408
PWMX (D/A) Control Register (DACR)
410
Peripheral Clock Select Register (PCSR)
411
Bus Master Interface
412
413
Operation
413
Section 10 16-Bit Free-Running Timer (FRT)
421
423
Register Descriptions
423
Output Compare Registers AR and AF (OCRAR and OCRAF)
424
Timer Interrupt Enable Register (TIER)
425
Timer Control/Status Register (TCSR)
426
Timer Control Register (TCR)
427
Timer Output Compare Control Register (TOCR)
428
Operation Timing
429
FRC Clear Timing
430
Timing of FRC Overflow Flag (OVF) Setting
431
Automatic Addition Timing
432
433
Usage Notes
433
Conflict between FRC Write and Increment
434
Conflict between OCR Write and Compare-Match
435
Switching of Internal Clock and FRC Operation
436
Section 11 8-Bit Timer (TMR)
439
442
Register Descriptions
442
Time Constant Register a (TCORA)
443
444
Timer Control Register (TCR)
444
447
Timer Control/Status Register (TCSR)
447
Timer Connection Register S (TCONRS)
451
452
Operation Timing
452
Timing of Counter Clear at Compare-Match
453
TMR_0 and TMR_1 Cascaded Connection
454
455
Interrupt Sources
455
456
Usage Notes
456
Conflict between TCNT Write and Increment
457
Conflict between TCOR Write and Compare-Match
458
Switching of Internal Clocks and TCNT Operation
459
Mode Setting with Cascaded Connection
460
Section 12 Watchdog Timer (WDT)
461
463
Input/Output Pins
463
464
Timer Control/Status Register (TCSR)
464
468
Operation
468
Interval Timer Mode
470
RESO Signal Output Timing
471
472
Interrupt Sources
472
473
Usage Notes
473
Conflict between Timer Counter (TCNT) Write and Increment
474
Switching between Watchdog Timer Mode and Interval Timer Mode
475
Section 13 Serial Communication Interface (SCI)
477
480
Input/Output Pins
480
Receive Shift Register (RSR)
481
Serial Mode Register (SMR)
482
Serial Control Register (SCR)
485
Serial Status Register (SSR)
488
Smart Card Mode Register (SCMR)
492
Bit Rate Register (BRR)
493
Operation in Asynchronous Mode
497
Data Transfer Format
498
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
499
Clock
500
SCI Initialization (Asynchronous Mode)
501
Serial Data Transmission (Asynchronous Mode)
502
Serial Data Reception (Asynchronous Mode)
504
Multiprocessor Communication Function
508
Multiprocessor Serial Data Transmission
510
Multiprocessor Serial Data Reception
511
Operation in Clock Synchronous Mode
514
SCI Initialization (Clock Synchronous Mode)
515
Serial Data Transmission (Clock Synchronous Mode)
516
Serial Data Reception (Clock Synchronous Mode)
519
Smart Card Interface Description
523
525
Block Transfer Mode
525
Receive Data Sampling Timing and Reception Margin
526
Initialization
527
Serial Data Transmission (Except in Block Transfer Mode)
528
Serial Data Reception (Except in Block Transfer Mode)
531
Clock Output Control
533
535
Interrupt Sources
535
Interrupts in Smart Card Interface Mode
536
537
Usage Notes
537
Restrictions on Using DTC
538
SCI Operations During Mode Transitions
539
Notes on Switching from SCK Pins to Port Pins
543
Section 14 CRC Operation Circuit (CRC)
545
546
Register Descriptions
546
CRC Data Input Register (CRCDIR)
547
Note on CRC Operation Circuit
551
Section 15 Serial Communication Interface with FIFO (SCIF)
553
555
Input/Output Pins
555
556
Register Descriptions
556
Receive Shift Register (FRSR)
557
Transmitter Holding Register (FTHR)
558
Interrupt Enable Register (FIER)
559
Interrupt Identification Register (FIIR)
560
FIFO Control Register (FFCR)
562
Line Control Register (FLCR)
563
Modem Control Register (FMCR)
564
Line Status Register (FLSR)
566
Modem Status Register (FMSR)
570
Scratch Pad Register (FSCR)
571
SCIF Control Register (SCIFCR)
572
574
Operation
574
Operation in Asynchronous Communication
575
Initialization of the SCIF
576
Data Transmission/Reception with Flow Control
579
Data Transmission/Reception through the LPC Interface
585
587
Interrupt Sources
587
Section 16 Serial Pin Multiplexed Modes
589
590
Input/Output Pins
590
591
Register Descriptions
591
Serial Multiplexed Mode Register 1 (SMR1)
592
Operation of Serial Pin Multiplexed Modes
593
Serial Pin Multiplexed Mode
594
595
Serial Pin Multiplexed Mode
595
596
Serial Pin Multiplexed Mode
596
Serial Port Pin Configuration
598
Section 17 Synchronous Serial Communication Unit (SSU)
599
601
Input/Output Pins
601
SS Control Register H (SSCRH)
602
SS Control Register L (SSCRL)
604
SS Mode Register (SSMR)
605
SS Enable Register (SSER)
606
SS Status Register (SSSR)
607
SS Control Register 2 (SSCR2)
609
SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3)
610
SS Receive Data Registers 0 to 3 (SSRDR0 to SSRDR3)
611
612
Operation
612
Relationship between Data Input/Output Pins and Shift Register
613
Communication Modes and Pin Functions
614
SSU Mode
616
SCS Pin Control and Conflict Error
624
Clock Synchronous Communication Mode
625
Interrupt Requests
631
Section 18 I 2 C Bus Interface (IIC)
633
636
Input/Output Pins
636
637
Register Descriptions
637
Slave Address Register (SAR)
638
Second Slave Address Register (SARX)
639
665
Operation
665
667
Initialization
667
Master Receive Operation
671
Slave Receive Operation
680
Slave Transmit Operation
688
IRIC Setting Timing and SCL Control
691
Operation Using the DTC
694
Noise Canceler
696
Interrupt Source
698
699
Usage Notes
699
Section 19 LPC Interface (LPC)
713
716
Input/Output Pins
716
717
Register Descriptions
717
Host Interface Control Registers 0 and 1 (HICR0 and HICR1)
719
Host Interface Control Registers 2 and 3 (HICR2 and HICR3)
727
Host Interface Control Register 4 (HICR4)
730
Host Interface Control Register 5 (HICR5)
731
Pin Function Control Register (PINFNCR)
732
LPC Channel 3 Address Register H, L (LADR3H, LADR3L)
734
Input Data Registers 1 to 3 (IDR1 to IDR3)
737
Bidirectional Data Registers 0 to 15 (TWR0 to TWR15)
738
Status Registers 1 to 3 (STR1 to STR3)
739
SERIRQ Control Register 0 (SIRQCR0)
747
SERIRQ Control Register 1 (SIRQCR1)
751
SERIRQ Control Register 2 (SIRQCR2)
755
SERIRQ Control Register 3 (SIRQCR3)
756
SERIRQ Control Register 4 (SIRQCR4)
757
SERIRQ Control Register 5 (SIRQCR5)
758
Host Interface Select Register (HISEL)
759
SCIF Address Register (SCIFADRH, SCIFADRL)
760
SMIC Flag Register (SMICFLG)
761
SMIC Control Status Register (SMICCSR)
762
SMIC Interrupt Register 0 (SMICIR0)
763
SMIC Interrupt Register 1 (SMICIR1)
765
BT Status Register 0 (BTSR0)
766
BT Status Register 1 (BTSR1)
769
BT Control Status Register 0 (BTCSR0)
772
BT Control Status Register 1 (BTCSR1)
773
BT Control Register (BTCR)
775
BT Data Buffer (BTDTR)
778
BT FIFO Valid Size Register 0 (BTFVSR0)
780
781
Operation
781
SMIC Mode Transfer Flow
783
BT Mode Transfer Flow
786
Gate A20
788
LPC Interface Shutdown Function (LPCPD)
791
LPC Interface Serialized Interrupt Operation (SERIRQ)
795
LPC Interface Clock Start Request
797
798
Interrupt Sources
798
SMI, HIRQ1, HIRQ3, HIRQ4, HIRQ5, HIRQ6, HIRQ7, HIRQ8, HIRQ9 HIRQ10, HIRQ11, HIRQ12, HIRQ13, HIRQ14, and HIRQ15
799
802
Usage Note
802
Section 20 Ethernet Controller (Etherc)
805
807
Input/Output Pins
807
Register Description
808
Etherc Mode Register (ECMR)
809
Etherc Status Register (ECSR)
812
Etherc Interrupt Permission Register (ECSIPR)
814
PHY Interface Register (PIR)
815
MAC Address High Register (MAHR)
816
Receive Frame Length Register (RFLR)
817
PHY Status Register (PSR)
818
Delayed Collision Detect Counter Register (CDCR)
819
CRC Error Frame Counter Register (CEFCR)
820
Too-Long Frame Receive Counter Register (TLFRCR)
821
IPG Register (IPGR)
822
Manual PAUSE Frame Set Register (MPR)
823
824
Operation
824
Reception
827
RMII Frame Timing
828
Accessing MII Registers
830
Magic Packet Detection
833
Operation by IPG Setting
834
836
Usage Notes
836
Operation Seed
837
839
Features
839
840
Register Descriptions
840
E-DMAC Mode Register (EDMR)
842
E-DMAC Transmit Request Register (EDTRR)
843
E-DMAC Receive Request Register (EDRRR)
844
Transmit Descriptor List Address Register (TDLAR)
845
Etherc/E-DMAC Status Register (EESR)
846
Etherc/E-DMAC Status Interrupt Permission Register (EESIPR)
851
Transmit/Receive Status Copy Enable Register (TRSCER)
854
Receive Missed-Frame Counter Register (RMFCR)
856
FIFO Depth Register (FDR)
858
Receiving Method Control Register (RMCR)
859
Receiving-Buffer Write Address Register (RBWAR)
860
Transmission-Descriptor Fetch Address Register (TDFAR)
861
Bit Rate Setting Register (ECBRR)
863
864
Operation
864
Transmission
874
876
Reception
876
Multi-Buffer Frame Transmit/Receive Processing
878
Section 22 USB Function Module (USB)
881
882
Input/Output Pins
882
883
Register Descriptions
883
Interrupt Flag Register 0 (IFR0)
884
Interrupt Flag Register 1 (IFR1)
886
Interrupt Flag Register 2 (IFR2)
887
Interrupt Select Register 0 (ISR0)
888
Interrupt Select Register 1 (ISR1)
889
Interrupt Enable Register 0 (IER0)
890
Interrupt Enable Register 2 (IER2)
891
Ep0O Data Register (Epdr0O)
892
EP1 Data Register (EPDR1)
893
Ep0O Receive Data Size Register (Epsz0O)
894
Data Status Register (DASTS)
896
FIFO Clear Register (FCLR)
897
DTC Transfer Setting Register (DMA)
898
Endpoint Stall Register (EPSTL)
901
Configuration Value Register (CVR)
902
Endpoint Information Register (EPIR)
904
Transceiver Test Register 0 (TRNTREG0)
908
Transceiver Test Register 1 (TRNTREG1)
909
911
Interrupt Sources
911
913
Operation
913
Operation at Cable Disconnection
914
Suspend and Resume Operations
915
Standby Mode
917
Control Transfer
920
EP1 Bulk-Out Transfer (Dual Fifos)
926
EP2 Bulk-In Transfer (Dual Fifos)
927
EP3 Interrupt-In Transfer
929
Processing of USB Standard Commands and Class/Vendor Commands
930
Stall Operations
931
Automatic Stall by USB Function Module
933
DTC Transfer
934
DTC Transfer for Endpoint 1
935
DTC Transfer for Endpoint 2
936
DTC Transfer End Interrupt
937
Example of USB External Circuitry
938
940
Usage Notes
940
Assigning Interrupt Sources to EP0
941
Restrictions on Peripheral Module Clock (Φ) Operating Frequency
942
Section 23 A/D Converter
943
945
Input/Output Pins
945
946
Register Descriptions
946
A/D Control/Status Register (ADCSR)
947
A/D Control Register (ADCR)
949
950
Operation
950
Scan Mode
951
Input Sampling and A/D Conversion Time
953
Timing of External Trigger Input
956
957
Interrupt Source
957
959
Usage Notes
959
Influences on Absolute Accuracy
960
Notes on Noise Countermeasures
961
Note on the Usage in Software Standby Mode
962
Section 24 RAM
963
Section 25 Flash Memory
965
Operating Mode
967
Mode Comparison
968
Flash Memory MAT Configuration
969
Programming/Erasing Interface
971
973
Input/Output Pins
973
974
Register Descriptions
974
Programming/Erasing Interface Register
976
Programming/Erasing Interface Parameter
984
On-Board Programming Mode
995
Boot Mode
996
USB Boot Mode
1000
User Program Mode
1004
User Boot Mode
1015
Procedure Program and Storable Area for Programming Data
1020
Protection
1030
Software Protection
1032
Switching between User MAT and User Boot MAT
1034
Programmer Mode
1035
Serial Communication Interface Specification for Boot Mode
1036
1064
Usage Notes
1064
Section 26 Boundary Scan (JTAG)
1067
1069
Input/Output Pins
1069
1070
Register Descriptions
1070
Instruction Register (SDIR)
1071
Bypass Register (SDBPR)
1072
ID Code Register (SDIDR)
1090
1091
Operation
1091
JTAG Reset
1092
1095
Usage Notes
1095
Section 27 Clock Pulse Generator
1099
Oscillator
1100
External Clock Input Method
1101
PLL Multiplier Circuit
1102
Clock Select Circuit
1103
1104
Usage Notes
1104
Section 28 Power-Down Modes
1105
1106
Register Descriptions
1106
Low-Power Control Register (LPWRCR)
1109
Mode Transitions and LSI States
1113
Medium-Speed Mode
1115
Sleep Mode
1116
Software Standby Mode
1117
Hardware Standby Mode
1119
Module Stop Mode
1120
Section 29 List of Registers
1121
Register Addresses (Address Order)
1122
Register Bits
1136
Register States in each Operating Mode
1154
Section 30 Platform Environment Control Interface (PECI)
1167
Absolute Maximum Ratings
1169
DC Characteristics
1170
AC Characteristics
1175
Control Signal Timing
1180
Bus Timing
1182
Multiplex Bus Timing
1191
Timing of On-Chip Peripheral Modules
1194
A/D Conversion Characteristics
1210
Flash Memory Characteristics
1211
1212
Usage Notes
1212
Appendix
1213
B. Product Lineup
1216
C. Package Dimensions
1217
Index
1219

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Renesas R4F2462 Hardware Manual (1230 pages)

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