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TE bit
SCK
output pin
TxD
Port
input/output
output pin
Port
Note: Initialized in software standby mode
Figure 13.36 Pin States during Transmission in Clock Synchronous Mode
Reception: Before making the transition to module stop or software standby mode, stop reception
(RE = 0). RSR, RDR, and SSR are reset. If transition is made during data reception, the data being
received will be invalid.
To receive data in the same reception mode after mode cancellation, set RE to 1, and then start
reception. To receive data in a different reception mode, initialize the SCI first.
Figure 13.37 shows a sample flowchart for mode transition during reception.
Transmission start
Marking output
SCI TxD output
(Internal Clock)
Section 13 Serial Communication Interface (SCI)
Transition to
Transmission end
software standby
mode
Last TxD bit retained
Rev. 1.00 Mar. 12, 2008 Page 493 of 1178
Software standby
mode cancelled
Port
input/output
Port input/output
High output*
SCI
Port
TxD output
REJ09B0403-0100
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