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Section 1 Overview
Type
Symbol
LPC
LAD3 to LAD0 P8, M9,
Interface
(LPC)
LFRAME
LRESET
LCLK
SERIRQ
LSCI,
LSMI,
PME
GA20
CLKRUN
LPCPD
Ethernet
RM_REF-CLK A13
controller
RM_TX-EN
(EtherC)
RM_TXD1
RM_TXD0
RM_CRS-DV C12
RM_RXD1
RM_RXD0
RM_RX-ER
MDC
MDIO
LNKSTA
EXOUT
WOL
Rev. 1.00 Mar. 12, 2008 Page 18 of 1178
REJ09B0403-0100
Pin No.
176-Pin
144-Pin
55 to 58
N9, R9
R8
54
N8
53
M8
52
R7
51
M11
66
P11
65
R11
64
N11
63
P10
62
R10
61
114
B12
115
C11
118
B11
119
113
D11
116
A12
117
B13
112
G15
92
93
G14
N1
34
M3
33
M4
35
I/O
Name and Function
Input/
Transfer cycle type/address/data I/O pins
Output
Input
Input pin indicating transfer cycle start
and forced termination
Input
LPC reset pin. When this pin is low, a
reset state is entered.
Input
PCI clock input pin
Input/
LPC serialized host interrupt request
Output
signal
Input/
LPC auxiliary output. Their functions are
Output
general I/O port.
Input/
GATE A20 control signal output pin; also
Output
used as the input pin for monitoring the
output state.
Input/
Input/output pin used to request starting
Output
the LCLK operation while LCLK is
stopped.
Input
Input pin used to control shutdown of the
LCP module
Input
Transmit/receive Clock
Output Transmit enable
Output
Transmit data
Output
Input
Carrier detection/receive data valid
Input
Receive data
Input
Input
Receive error
Input
Management data clock
Input/
Management data I/O
Output
Input
Link status
Output General-purpose external output
Output Wake-on-LAN
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