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19.3.16 SERIRQ Control Register 4 (SIRQCR4)
SIRQCR4 controls LPC interrupt requests to the host.
Initial
Bit
Bit Name
Value
7
IRQ15E
0
6
IRQ14E
0
5
IRQ13E
0
4
IRQ8E
0
3
IRQ7E
0
2
IRQ5E
0
1
IRQ4E
1
0
IRQ3E
1
R/W
Slave Host Description
R/W
Host IRQ15 Interrupt Enable
0: Disables HIRQ15 interrupt request by IRQ15E
1: Enables HIRQ15 interrupt request
R/W
Host IRQ14 Interrupt Enable
0: Disables HIRQ14 interrupt request by IRQ14E
1: Enables HIRQ14 interrupt request
R/W
Host IRQ13 Interrupt Enable
0: Disables HIRQ13 interrupt request by IRQ13E
1: Enables HIRQ13 interrupt request
R/W
Host IRQ8 Interrupt Enable
0: Disables HIRQ8 interrupt request by IRQ8E
1: Enables HIRQ8 interrupt request
R/W
Host IRQ7 Interrupt Enable
0: Disables HIRQ7 interrupt request by IRQ7E
1: Enables HIRQ7 interrupt request
R/W
Host IRQ5 Interrupt Enable
0: Disables HIRQ5 interrupt request by IRQ5E
1: Enables HIRQ5 interrupt request
R/W
Host IRQ4 Interrupt Enable
0: Disables HIRQ4 interrupt request by IRQ4E
1: Enables HIRQ4 interrupt request
R/W
Host IRQ3 Interrupt Enable
0: Disables HIRQ3 interrupt request by IRQ3E
1: Enables HIRQ3 interrupt request
Section 19 LPC Interface (LPC)
Rev. 1.00 Mar. 12, 2008 Page 709 of 1178
REJ09B0403-0100
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