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Section 6 Bus Controller (BSC)
(2)
8-Bit, 3-State Access Space
Figure 6.6 shows the bus timing for an 8-bit, 3-state access space. When an 8-bit access space is
accessed, the upper half (D15 to D8) of the data bus is used. Wait states can be inserted.
IOS (IOSE = 1)
CS256 (CS256E = 1)
AS (IOSE = 0)
Read
Write
Note:
* For external address space access, this signal is not output when the 256-Kbyte extended area
is accessed with CS256E = 1.
Figure 6.6 Bus Timing for 8-Bit, 3-State Access Space
Rev. 1.00 Mar. 12, 2008 Page 130 of 1178
REJ09B0403-0100
φ
Address bus
*
RD
D15 to D8
D7 to D0
HWR
D15 to D8
Bus cycle
T
T
1
2
Valid
T
3
Valid
Invalid
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