Renesas H8S Family Hardware Manual page 954

Section 23 A/D Converter
φ
Address
Write signal
Input sampling
timing
ADF
[Legend]
(1): ADCSR write cycle
(2): ADCSR address
t : A/D conversion start delay
D
t : Input sampling time
SPL
t : A/D conversion time
CONV
Rev. 1.00 Mar. 12, 2008 Page 906 of 1178
REJ09B0403-0100
(1)
(2)
t
t
SPL
D
t
Figure 23.4 A/D Conversion Timing
CONV