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11.2.5
Timer Control/Status Register (TCSR)
TCSR indicates the status flags and controls compare-match output. See section 11.2.6, Timer
Connection Register S (TCONRS) for details on the TCSR_Y and TCSR_X accesses.
• TCSR_0
Bit
Bit Name
7
CMFB
6
CMFA
5
OVF
4
ADTE
3 to 0
Note:
* Only 0 can be written to clear the flag.
Initial
Value
R/W
Description
0
R/(W)* Compare-Match Flag B
[Setting condition]
When the values of TCNT_0 and TCORB_0 match
[Clearing condition]
Read CMFB when CMFB = 1, then write 0 in CMFB
0
R/(W)* Compare-Match Flag A
[Setting condition]
When the values of TCNT_0 and TCORA_0 match
[Clearing condition]
Read CMFA when CMFA = 1, then write 0 in CMFA
0
R/(W)* Timer Overflow Flag
[Setting condition]
When TCNT_0 overflows from H'FF to H'00
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
0
R/W
A/D Trigger Enable
Selects whether the A/D conversion start request on
compare match A is enabled or disabled.
0: A/D conversion start request is disabled
1: A/D conversion start request is enabled
All 1
R
Reserved
These bits are always read as 1 and cannot be modified.
Section 11 8-Bit Timer (TMR)
Rev. 1.00 Mar. 12, 2008 Page 399 of 1178
REJ09B0403-0100
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