Page 1 H8S/2437 Group Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S / 2600 Series H8S/2437 HD64F2437 Rev.1.00 2003.9.19...
Page 2 Rev.1.00, 09/03, page ii of xxxviii...
Page 3 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination.
Page 4: General Precautions On Handling Of Product
General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed.
Page 5 Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module.
Page 6: Preface
Preface This LSI is a microcomputer (MCU) made up of the H8S/2600 CPU with Renesas Technology- original architecture as its core, and the peripheral functions required to configure a system. The H8S/2600 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a simple and optimized instruction set for high-speed operation.
Page 7: List Of Registers
Please ensure you have the latest versions of all documents you require. http://www.renesas.com/eng/ H8S/2437 Group manuals: Document Title Document No. H8S/2437 Group Hardware Manual This manual H8S/2600 Series, H8S/2000 Series Programming Manual ADE-602-083 User's manuals for development tools: Document Title Document No.
Page 8 Rev.1.00, 09/03, page viii of xxxviii...
Page 9: Table Of Contents
Contents Section 1 Overview................... 1 Features ..........................1 Internal Block Diagram..................... 2 Pin Description........................3 1.3.1 Pin Assignment ....................3 1.3.2 Pin Assignment in Each Operating Mode............4 1.3.3 Pin Functions .......................9 Section 2 CPU....................15 Features ..........................15 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU ........16 2.1.2 Differences from H8/300 CPU................17 2.1.3...
Page 10 2.7.8 Memory Indirect—@@aa:8 ................45 2.7.9 Effective Address Calculation ................46 Processing States....................... 49 Usage Note........................50 2.9.1 Usage Notes on Bit-Wise Operation Instructions ..........50 Section 3 MCU Operating Modes ..............51 Operating Mode Selection ....................51 Register Descriptions ......................52 3.2.1 Mode Control Register (MDCR) .................
Page 11 Interrupt Control Modes and Interrupt Operation .............81 5.6.1 Interrupt Control Mode 0 ..................81 5.6.2 Interrupt Control Mode 2 ..................83 5.6.3 Interrupt Exception Handling Sequence ..............85 5.6.4 Interrupt Response Times ..................87 Usage Notes ........................88 5.7.1 Contention between Interrupt Generation and Disabling........88 5.7.2 Instructions that Disable Interrupts ..............89 5.7.3...
Page 12 7.2.6 Port 1 Input Pull-Up MOS States................. 142 Port 2..........................143 7.3.1 Port 2 Data Direction Register (P2DDR)............. 143 7.3.2 Port 2 Data Register (P2DR)................144 7.3.3 Port 2 Register (PORT2)..................144 7.3.4 Port 2 Pull-Up MOS Control Register (P2PCR)..........145 7.3.5 Pin Functions .......................
Page 13 7.10.2 Port 9 Data Register (P9DR)................190 7.10.3 Port 9 Register (PORT9)..................190 7.10.4 Port Function Control Register (PFCR) ...............191 7.10.5 Pin Functions .......................192 7.11 Port A ..........................198 7.11.1 Port A Data Direction Register (PADDR) ............198 7.11.2 Port A Data Register (PADR) ................199 7.11.3 Port A Register (PORTA) ..................199 7.11.4 Pin Functions .......................200 7.12 Port B ..........................205...
Page 14 Bus Master Interface ......................231 Operation .......................... 233 Section 10 16-Bit Free-Running Timer (FRT)..........239 10.1 Features..........................239 10.2 Input/Output Pins ......................241 10.3 Register Descriptions ......................241 10.3.1 Free-Running Counter (FRC) ................242 10.3.2 Output Compare Registers A and B (OCRA and OCRB) ........242 10.3.3 Input Capture Registers A to D (ICRA to ICRD) ..........
Page 15 11.3.4 Timer Control Register (TCR) ................274 11.3.5 Timer Control/Status Register (TCSR) ..............277 11.3.6 Input Capture Register (TICR) ................282 11.3.7 Time Constant Register (TCORC)...............282 11.3.8 Input Capture Registers R and F (TICRR and TICRF)........282 11.3.9 Timer Input Select Register (TISR) ..............283 11.4 Operation...........................283 11.4.1 Pulse Output......................283 11.5 Operation Timing......................284...
Page 16 12.3.9 Timer Synchro Register (TSYR) ................. 324 12.4 Interface to Bus Master ..................... 325 12.4.1 16-Bit Registers ....................325 12.4.2 8-Bit Registers ..................... 325 12.5 Operation .......................... 327 12.5.1 Basic Functions....................327 12.5.2 Synchronous Operation..................332 12.5.3 Buffer Operation ....................334 12.5.4 Cascaded Operation .....................
Page 17 Section 14 Duty Measurement Circuit.............. 399 14.1 Features ..........................399 14.2 Input/Output Pins ......................401 14.3 Register Descriptions ......................402 14.3.1 Free-Running Counter (TWCNT)................402 14.3.2 Input Capture Register (TWICR).................402 14.3.3 Duty Measurement Control Register 1 (TWCR1) ..........403 14.3.4 Duty Measurement Control Register 2 (TWCR2) ..........404 14.4 Operation...........................406 14.4.1 Duty Measurement for External Event Signal .............406 14.5 Operation Timing......................407...
Page 18 Section 16 Serial Communication Interface (SCI) ..........425 16.1 Features..........................425 16.2 Input/Output Pins ......................427 16.3 Register Descriptions ......................428 16.3.1 Receive Shift Register (RSR) ................428 16.3.2 Receive Data Register (RDR) ................428 16.3.3 Transmit Data Register (TDR)................428 16.3.4 Transmit Shift Register (TSR) ................
Page 19 Section 17 I C Bus Interface 3 (IIC3) ............... 475 17.1 Features ..........................475 17.2 Input/Output Pins ......................478 17.3 Register Descriptions ......................478 17.3.1 I C Bus Control Register A (ICCRA) ..............479 17.3.2 I C Bus Control Register B (ICCRB)..............480 17.3.3 I C Bus Mode Register (ICMR) ................482 17.3.4 I C Bus Interrupt Enable Register (ICIER) ............483...
Page 20 18.7.1 Module Stop Mode Setting .................. 520 18.7.2 Permissible Signal Source Impedance ..............520 18.7.3 Influences on Absolute Accuracy ................ 521 18.7.4 Setting Range of Analog Power Supply and Other Pins ........521 18.7.5 Notes on Board Design ..................521 18.7.6 Notes on Noise Countermeasures ................
Page 21 21.5.1 Note on Resonator....................617 21.5.2 Notes on Board Design ..................617 21.5.3 Notes on Operation Confirmation................618 Section 22 Power-Down Modes ............... 619 22.1 Register Descriptions ......................622 22.1.1 Standby Control Register (SBYCR) ..............622 22.1.2 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL)....624 22.1.3 Extension Module Stop Control Registers H and L (EXMSTPCRH, EXMSTPCRL) .................625 22.2 Operation...........................626...
Page 22 Appendix ......................695 I/O Port States in Each Pin State..................695 Product Lineup........................697 Package Dimensions ......................698 Index ......................699 Rev.1.00, 09/03, page xxii of xxxviii...
Page 23 Figures Section 1 Overview Figure 1.1 Internal Block Diagram of H8S/2437 Group..............2 Figure 1.2 Pin Assignment of H8S/2437 Group (FP-128B) ............3 Figure 1.3 Sample Design of Reset Signals without Affection Each Other........14 Section 2 CPU Figure 2.1 Exception-Handling Vector Table (Normal Mode).............19 Figure 2.2 Stack Structure in Normal Mode .................19...
Page 24 Figure 6.6 Bus Timing for 8-Bit, 3-State Access Space ............. 106 Figure 6.7 Bus Timing for 16-Bit, 2-State Access Space (Even Byte Access)......107 Figure 6.8 Bus Timing for 16-Bit, 2-State Access Space (Odd Byte Access) ......108 Figure 6.9 Bus Timing for 16-Bit, 2-State Access Space (Word Access) ........109 Figure 6.10 Bus Timing for 16-Bit, 3-State Access Space (Even Byte Access)......
Page 25 Section 10 16-Bit Free-Running Timer (FRT) Figure 10.1 Block Diagram of 16-Bit Free-Running Timer ............240 Figure 10.2 Example of Pulse Output..................251 Figure 10.3 Increment Timing with Internal Clock Source ............252 Figure 10.4 Increment Timing with External Clock Source ............252 Figure 10.5 Timing of Output Compare A Output ..............253 Figure 10.6 Clearing of FRC by Compare-Match A Signal ............253 Figure 10.7 Timing of Input Capture Input Signal (Usual Case)..........254 Figure 10.8 Timing of Input Capture Input Signal (When ICRA to ICRD are Read) ....254...
Page 26 Section 12 16-Bit Timer Pulse Unit (TPU) Figure 12.1 Block Diagram of TPU.................... 300 Figure 12.2 16-Bit Register Access Operation [Bus Master ↔ TCNT (16 Bits)] ...... 325 Figure 12.3 8-Bit Register Access Operation [Bus Master ↔ TCR (Upper 8 Bits)]....325 Figure 12.4 8-Bit Register Access Operation [Bus Master ↔...
Page 27 Figure 12.42 TGI Interrupt Timing (Input Capture) ..............355 Figure 12.43 TCIV Interrupt Setting Timing................355 Figure 12.44 TCIU Interrupt Setting Timing................356 Figure 12.45 Timing for Status Flag Clearing by CPU...............356 Figure 12.46 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode ....357 Figure 12.47 Contention between TCNT Write and Clear Operations ........358 Figure 12.48 Contention between TCNT Write and Increment Operations .......358 Figure 12.49 Contention between TGR Write and Compare Match...........359...
Page 28 Figure 14.9 Set Timing for OVF Flag ..................410 Figure 14.10 TWCNT Write-Increment Conflict ............... 411 Figure 14.11 Write to START Bit during Free-Running Counter Operation ......411 Section 15 Watchdog Timer (WDT) Figure 15.1 Block Diagram of WDT ..................417 Figure 15.2 Watchdog Timer Mode (RST/NMI = 1) Operation..........
Page 29 Figure 16.23 Pin States during Transmission in Clocked Synchronous Mode (Internal Clock) .....................471 Figure 16.24 Sample Flowchart for Mode Transition during Reception ........472 Figure 16.25 Switching from SCK Pins to Port Pins ..............473 Figure 16.26 Prevention of Low Pulse Output at Switching from SCK Pins to Port Pins..473 Section 17 I C Bus Interface 3 (IIC3) Figure 17.1 Block Diagram of I...
Page 30 Figure 20.9 Overview of Programming/Erasing Flow..............555 Figure 20.10 RAM Map when Programming/Erasing is Executed ..........556 Figure 20.11 Programming Procedure..................557 Figure 20.12 Erasing Procedure....................562 Figure 20.13 Repeating Procedure of Erasing and Programming..........564 Figure 20.14 Procedure for Programming User MAT in User Boot Mode ........ 566 Figure 20.15 Procedure for Erasing User MAT in User Boot Mode ..........
Page 31 Figure 24.13 Multiplex Bus Timing/3-State Access with One Wait State........684 Figure 24.14 I/O Port Input/Output Timing................686 Figure 24.15 FRT Input/Output Timing ..................686 Figure 24.16 FRT Clock Input Timing ..................686 Figure 24.17 TPU Input/Output Timing ..................687 Figure 24.18 TPU Clock Input Timing..................687 Figure 24.19 8-Bit Timer Output Timing ...................687 Figure 24.20 8-Bit Timer Clock Input Timing................687 Figure 24.21 8-Bit Timer Reset Input Timing ................688...
Page 32 Rev. 1.00, 09/03, page xxxii of xxxviii...
Page 33 Tables Section 1 Overview Table 1.1 Pin Assignment in Each Operating Mode..............4 Table 1.2 Pin Functions ........................9 Section 2 CPU Table 2.1 Instruction Classification ....................31 Table 2.2 Operation Notation......................32 Table 2.3 Data Transfer Instructions...................33 Table 2.4 Arithmetic Operations Instructions (1) ...............34 Table 2.4 Arithmetic Operations Instructions (2) ...............35 Table 2.5...
Page 34 Table 6.4 Address Range and External Address Area (Multiplex Extended Mode)....99 Table 6.5 Bus Specifications for Multiplex Extended Bus Interface (Address Cycle) ....99 Table 6.6 Bus Specifications for Multiplex Extended Bus Interface (Data Cycle)..... 99 Table 6.7 Data Buses Used and Valid Strobes................104 Table 6.8 Pin States in Idle Cycle .....................
Page 35 Section 12 16-Bit Timer Pulse Unit (TPU) Table 12.1 TPU Functions ......................301 Table 12.2 Pin Configuration....................303 Table 12.3 CCLR2 to CCLR0 (Channel 0)................306 Table 12.4 CCLR2 to CCLR0 (Channels 1 and 2) ..............306 Table 12.5 TPSC2 to TPSC0 (Channel 0) ................307 Table 12.6 TPSC2 to TPSC0 (Channel 1) ................307 Table 12.7...
Page 36 Section 14 Duty Measurement Circuit Table 14.1 Pin Configuration....................401 Table 14.2 Interrupt Sources for Duty Measurement Circuit..........410 Table 14.3 Switching of Internal Clock and TWCNT Operation ........... 412 Table 14.4 Switching of External Event Signal and Operation of Edge Detection Circuit..414 Section 15 Watchdog Timer (WDT) Table 15.1 Interrupt Source ....................
Page 37 Table 20.6 System Clock Frequency for Automatic-Bit-Rate Adjustment......553 Table 20.7 Executable MAT ....................569 Table 20.8 (1) Usable Area for Programming in User Program Mode........570 Table 20.8 (2) Usable Area for Erasure in User Program Mode ..........572 Table 20.8 (3) Usable Area for Programming in User Boot Mode...........574 Table 20.8 (4) Usable Area for Erasure in User Boot Mode ............576 Table 20.9...
Page 38 Rev. 1.00, 09/03, page xxxviii of xxxviii...
Page 39: Section 1 Overview
Section 1 Overview Features • High-speed H8S/2600 central processing unit with an internal 16-bit architecture Upward-compatible with H8/300 and H8/300H CPUs on an object level Sixteen 16-bit general registers 69 basic instructions Multiply-and-accumulate instruction • Various peripheral functions 8-bit PWM timer (PWM) 14-bit PWM timer (PWMX) 16-bit free-running timer (FRT) 8-bit timer (TMR)
Page 40: Internal Block Diagram
Internal Block Diagram Figure 1.1 shows the internal block diagram of the H8S/2437 Group. P00/AN8 P50/SCK0 P01/AN9 P51/TxD0 P02/AN10 P52/RxD0 P03/AN11 P53/SCK1 P04/AN12/ P54/TxD1 P05/AN13/ P55/RxD1 H8S/2600 CPU P06/AN14/ P56/TMO0_1/ExPW4 P07/AN15/ P57/TMO1_1/ExPW5 P10/PW0/A0/AD0 P60/FTOA_1/D0 P11/PW1/A1/AD1 P61/FTOB_1/D1 Bus controller P12/PW2/A2/AD2 P62/TMOX_1/D2...
Page 41: Pin Description
Pin Description 1.3.1 Pin Assignment Figure 1.2 shows the pin assignment of the H8S/2437 Group. P01/AN9 PC0/SCL2 PC1/SDA2 P00/AN8 P77/AN7 PC2/SCL3 P76/AN6 PC3/SDA3 P27/TIOCB2/TCLKD/A15/AD15 P75/AN5 P74/AN4 P26/TIOCA2/A14/AD14 P25/TIOCB1/TCLKC/A13/AD13 P73/AN3 P72/AN2 P24/TIOCA1/A12/AD12 P71/AN1 P23/TIOCD0/TCLKB/A11/AD11 P22/TIOCC0/TCLKA/A10/AD10 P70/AN0 AVSS P21/TIOCB0/A9/AD9 P20/TIOCA0/A8/AD8 FP-128B P43/...
Page 42: Pin Assignment In Each Operating Mode
1.3.2 Pin Assignment in Each Operating Mode Table 1.1 Pin Assignment in Each Operating Mode Pin Name Extended Mode (EXPE = 1) Single-Chip Mode QFP- Flash Memory Programmer Mode Normal Multiplex (EXPE = 0) P33/ExIRQ3 P33/ExIRQ3 P32/ExIRQ2 P32/ExIRQ2 P31/ExIRQ1 P31/ExIRQ1 P30/ExIRQ0 P30/ExIRQ0 P67/RxD2...
Page 43 Pin Name Extended Mode (EXPE = 1) Single-Chip Mode QFP- Flash Memory Programmer Mode Normal Multiplex (EXPE = 0) EXTAL EXTAL EXTAL XTAL XTAL XTAL ETMS/PC4* ETMS/PC4* ETCK/PC5* ETCK/PC5* STBY STBY ETDI/PC6* ETDI/PC6* ETRST ETRST ETDO/PC7* ETDO/PC7* P50/SCK0 P50/SCK0 P51/TxD0 P51/TxD0 P52/RxD0 P52/RxD0...
Page 44 Pin Name Extended Mode (EXPE = 1) Single-Chip Mode QFP- Flash Memory Programmer Mode Normal Multiplex (EXPE = 0) P74/AN4 P74/AN4 P75/AN5 P75/AN5 P75/AN6 P75/AN6 P77/AN7 P77/AN7 P00/AN8 P00/AN8 P01/AN9 P01/AN9 P02/AN10 P02/AN10 P03/AN11 P03/AN11 P04/AN12/ExIRQ4 P04/AN12/ExIRQ4 P05/AN13/ExIRQ5 P05/AN13/ExIRQ5 P06/AN14/ExIRQ6 P06/AN14/ExIRQ6 P07/AN15/ExIRQ7 P07/AN15/ExIRQ7...
Page 45 Pin Name Extended Mode (EXPE = 1) Single-Chip Mode QFP- Flash Memory Programmer Mode Normal Multiplex (EXPE = 0) P84/PWX0 P84/PWX0 PA7/CS3/ExTIOCA1 PA7/ExTIOCA1 PA6/FTCI_0/HFBACKI PA6/FTCI_0/HFBACKI PA5/FTIB_0/VFBACKI PA5/FTIB_0/VFBACKI PA4/FTIC_0/CLAMPO PA4/FTIC_0/CLAMPO PA3/FTOB_0/CBLANK PA3/FTOB_0/CBLANK PA2/TMO0_0/ExTIOCC0/ PA2/TMO0_0/ExTIOCC0/ ExTCLKA ExTCLKA PA1/TMOY_0/ExPW7/SCK4 PA1/TMOY_0/ExPW7/SCK4 NC PA0/TMOX_0/ExPW6/SCK3 PA0/TMOX_0/ExPW6/SCK3 VCC P83/SDA1/RxD4 P83/SDA1/RxD4 P82/SCL1/TxD4...
Page 46 Pin Name Extended Mode (EXPE = 1) Single-Chip Mode QFP- Flash Memory Programmer Mode Normal Multiplex (EXPE = 0) P14/A4 P14/PW4 P13/A3 P13/PW3 P12/A2 P12/PW2 P11/A1 P11/PW1 P10/A0 P10/PW0 Note: * Not supported by the on-chip emulator. Rev. 1.00, 09/03, page 8 of 704...
Page 47: Pin Functions
1.3.3 Pin Functions Table 1.2 Pin Functions Type Symbol Pin No. Name and Function Power 16, 31, Input Power supply pins. Connect all these pins to the supply 83, 115 system power supply. Input External capacitance pin for internal step-down power.
Page 48: Manual
Type Symbol Pin No. Name and Function WAIT Bus control Input Requests insertion of a wait state in the bus cycle when accessing an external 3-state address space. Output This pin is low when the external address space is being read. Output This pin is low when the external address space is to be written to, and the upper half of the data bus is enabled.
Page 49 Type Symbol Pin No. Name and Function 14-bit PWM PWX0 Output Pulse output pins for PWM D/A timer PWX1 (PWMX) 16-bit free- FTCI_0 Input External event input pins running FTCI_1 timer (FRT) FTOA_0 Output Output compare output pins FTOA_1 FTOB_0 FTOB_1 FTIA_0 to 84, 93,...
Page 50 Type Symbol Pin No. Name and Function 16-bit timer TCLKA to 107, 109, Input External clock input pins. Selectable to which pin pulse unit TCLKD 111, 112 of TCLKn or ExTCLKn to input external clocks. (TPU) ExTCLKA to 96, 22, ExTCLKD 14, 17 TIOCA0...
Page 51 Type Symbol Pin No. Name and Function C bus SCL0, SCL1 102, 100 C clock input/output pins. These pins can drive interface 3 SCL2, SCL3 103, 105 a bus directly with the NMOS open drain output. (IIC3) SDA0, SDA1 101, 99 C data input/output pins.
Page 52: Figure 1.3 Sample Design Of Reset Signals Without Affection Each Other
Notes: 1. Not supported by the on-chip emulator. 2. Following precautions are required on the power-on reset signal that is applied to the ETRST pin. The reset signal must be applied at a power-on. Apart the power-on reset circuit from this LSI to prevent the ETRST pin of the board tester from affecting the operation of this LSI.
Page 53: Section 2 Cpu
Section 2 CPU The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. This section describes the H8S/2600 CPU.
Page 54: Differences Between H8S/2600 Cpu And H8S/2000 Cpu
• Two CPU operating modes Normal mode* Advanced mode • Power-down state Transition to power-down state by SLEEP instruction CPU clock speed selection Note: Normal mode is not available in this LSI. 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.
Page 55: Differences From H8/300 Cpu
2.1.2 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2600 CPU has the following enhancements. • More general registers and control registers Eight 16-bit expanded registers, and one 8-bit and two 32-bit control registers, have been added. •...
Page 56: Cpu Operating Modes
CPU Operating Modes The H8S/2600 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space. The mode is selected by the mode pins. 2.2.1 Normal Mode The exception-handling vector table and stack have the same structure as in the H8/300 CPU.
Page 57: Figure 2.1 Exception-Handling Vector Table (Normal Mode)
H'0000 Reset exception-handling vector H'0001 H'0002 (Reserved for system use) H'0003 H'0004 H'0005 (Reserved for system use) H'0006 Exception-handling vector table H'0007 H'0008 Exception-handling vector 1 H'0009 H'000A Exception-handling vector 2 H'000B Figure 2.1 Exception-Handling Vector Table (Normal Mode) EXR* (16 bits) Reserved* (SP *...
Page 58: Advanced Mode
2.2.2 Advanced Mode • Address Space Linear access is provided to a 16-Mbyte maximum address space. • Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. •...
Page 59: Figure 2.4 Stack Structure In Advanced Mode
In advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the first part of this range is also used for the exception-handling vector table.
Page 60: Address Space
Address Space Figure 2.5 shows a memory map of the H8S/2600 CPU. The H8S/2600 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces differ depending on the product.
Page 61: Registers
Registers The H8S/2600 CPU has the internal registers shown in figure 2.6. There are two types of registers: general registers and control registers. Control registers are a 24-bit program counter (PC), an 8-bit extended register (EXR), an 8-bit condition code register (CCR), and a 64-bit multiply-accumulate register (MAC).
Page 62: General Registers
2.4.1 General Registers The H8S/2600 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the usage of the general registers.
Page 63: Program Counter (Pc)
Free area SP (ER7) Stack area Figure 2.8 Stack 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0.) 2.4.3 Extended Register (EXR)
Page 64: Condition-Code Register (Ccr)
2.4.4 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions.
Page 65: Multiply-Accumulate Register (Mac)
Bit Name Initial Value R/W Description Undefined Overflow Flag Set to 1 when an arithmetic overflow occurs, and cleared to 0 otherwise. Undefined Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: • Add instructions, to indicate a carry •...
Page 66: Data Formats
Data Formats The H8S/2600 CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data.
Page 67: Figure 2.9 General Register Data Formats (2)
Data Type Register Number Data Format Word data Word data Longword data [Legend] ERn: General register ER General register E General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB : Least significant bit Figure 2.9 General Register Data Formats (2) Rev.
Page 68: Memory Data Formats
2.5.2 Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2600 CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address.
Page 69: Instruction Set
Instruction Set The H8S/2600 CPU has 69 types of instructions. The instructions are classified by function in table 2.1. Table 2.1 Instruction Classification Function Instructions Size Types Data transfer B/W/L POP* , PUSH* LDM, STM MOVFPE* , MOVTPE* Arithmetic ADD, SUB, CMP, NEG B/W/L operations ADDX, SUBX, DAA, DAS...
Page 70: Table Of Instructions Classified By Function
2.6.1 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.2 Operation Notation Symbol Description General register (destination)* General register (source)* General register* General register (32-bit register) Multiply-accumulate register (32-bit register)
Page 71: Table 2.3 Data Transfer Instructions
Table 2.3 Data Transfer Instructions Instruction Size* Function (EAs) → Rd, Rs → (EAd) B/W/L Transfers data between two general registers or between a general register and memory, or transfers immediate data to a general register. MOVFPE Cannot be used in this LSI. MOVTPE Cannot be used in this LSI.
Page 72: Table 2.4 Arithmetic Operations Instructions (1)
Table 2.4 Arithmetic Operations Instructions (1) Instruction Size* Function Rd ± Rs → Rd, Rd ± #IMM → Rd B/W/L Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from byte data in a general register.
Page 73: Table 2.4 Arithmetic Operations Instructions (2)
Table 2.4 Arithmetic Operations Instructions (2) Instruction Size* Function Rd ÷ Rs → Rd DIVXS Performs signed division on data in two general registers. Either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder. B/W/L Rd –...
Page 74: Table 2.5 Logic Operations Instructions
Table 2.5 Logic Operations Instructions Instruction Size* Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd B/W/L Performs a logical AND operation on a general register and another general register or immediate data. Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd B/W/L Performs a logical OR operation on a general register and another general register or immediate data.
Page 75: Table 2.7 Bit Manipulation Instructions (1)
Table 2.7 Bit Manipulation Instructions (1) Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
Page 76: Table 2.7 Bit Manipulation Instructions (2)
Table 2.7 Bit Manipulation Instructions (2) Instruction Size* Function C ⊕ (<bit-No.> of <EAd>) → C BXOR Exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ⊕...
Page 77: Table 2.8 Branch Instructions
Table 2.8 Branch Instructions Instruction Size Function — Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic Description Condition BRA (BT) Always (true) Always BRN (BF) Never (false) Never C ∨ Z = 0 High C ∨...
Page 78: Table 2.9 System Control Instructions
Table 2.9 System Control Instructions Instruction Size* Function TRAPA — Starts trap-instruction exception handling. — Returns from an exception-handling routine. SLEEP — Causes a transition to a power-down state. (EAs) → CCR, (EAs) → EXR Transfers the contents of a general register or memory, or immediate data to CCR or EXR.
Page 79: Basic Instruction Formats
Table 2.10 Block Data Transfer Instructions Instruction Size Function if R4L ≠ 0 then EEPMOV.B — Repeat @ER5+ → @ER6+ R4L–1 → R4L Until R4L = 0 else next; if R4 ≠ 0 then EEPMOV.W — Repeat @ER5+ → @ER6+ R4–1 →...
Page 80: Figure 2.11 Instruction Formats (Examples)
• Operation Field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. •...
Page 81: Addressing Modes And Effective Address Calculation
Addressing Modes and Effective Address Calculation The H8S/2600 CPU supports the eight addressing modes listed in table 2.11. The usable address modes are different in each instruction. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect.
Page 82: Register Indirect With Post-Increment Or Pre-Decrement-@Ern+ Or @-Ern
2.7.4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn Register indirect with post-increment—@ERn+: The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register.
Page 83: Immediate-#Xx:8, #Xx:16, Or #Xx:32
2.7.6 Immediate—#xx:8, #xx:16, or #xx:32 The instruction code contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number.
Page 84: Effective Address Calculation
Specified Specified Reserved Branch address by @aa:8 by @aa:8 Branch address (a) Normal Mode (a) Advanced Mode Note: * Normal mode is not available in this LSI. Figure 2.12 Branch Address Specification in Memory Indirect Mode 2.7.9 Effective Address Calculation Table 2.13 indicates how effective addresses (EA) are calculated in each addressing mode.
Page 85: Table 2.13 Effective Address Calculation (1)
Table 2.13 Effective Address Calculation (1) Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Register direct (Rn) Operand is general register contents. Register indirect (@ERn) General register contents General register contents Sign extension Register indirect with post-increment or pre-decrement •Register indirect with post-increment @ERn+ General register contents...
Page 86: Table 2.13 Effective Address Calculation (2)
Table 2.13 Effective Address Calculation (2) Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Absolute address Sign extension Immediate Operand is immediate data. PC contents Sign extension Memory contents Memory contents Note: * Normal mode is not available in this LSI. Rev.
Page 87: Processing States
Processing States The H8S/2600 CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and program stop state. Figure 2.13 indicates the state transitions. • Reset State The CPU and on-chip peripheral modules are all initialized and stop. When the RES input goes low, all current processing stops and the CPU enters the reset state.
Page 88: Usage Note
End of bus request Bus request Program execution state Bus-released state Sleep mode External interrupt request Exception Software standby handling state mode = High = High, = Low Hardware standby Reset state mode Reset state Power down state Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever goes low.
Page 89: Section 3 Mcu Operating Modes
Section 3 MCU Operating Modes Operating Mode Selection This LSI has four operating modes (modes 1, 3, 5, and 7). These modes are determined by the mode pin settings (MD2, MD1, and MD0). For normal program execution mode, the mode pins must be set to mode 7.
Page 90: Register Descriptions
Register Descriptions The following registers are related to the operating mode. • Mode control register (MDCR) • System control register (SYSCR) 3.2.1 Mode Control Register (MDCR) MDCR monitors the current operating mode and operating mode settings. Bit Name Initial Value Descriptions EXPE Extended Mode Enable...
Page 91: System Control Register (Syscr)
3.2.2 System Control Register (SYSCR) SYSCR selects saturating calculation for the MAC instruction, and controls reset source monitor, Ram address space, and on-chip flash memory control. Bit Name Initial Value Descriptions MACS MAC Saturation Selects either saturating or non-saturating calculation for the MAC instruction.
Page 92: Operating Mode Descriptions
Operating Mode Descriptions 3.3.1 Mode 7 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. The initial mode after a reset is single-chip mode, to use the external address space, set the EXPE bit in MDCR to 1.
Page 93: Pin Functions
3.3.2 Pin Functions The pin functions of ports 1 to 3, 6, 9, and A change according to operating modes. Table 3.2 shows the pin functions in each operating mode. Table 3.2 Pin Functions in Each Operating Mode Mode 7 Port Normal Extended Mode Multiplex Extended Mode...
Page 94: Memory Map
Memory Map Figure 3.1 shows a memory map. ROM : 256 kbytes, RAM : 16 kbytes ROM : 256kbytes, RAM : 16kbytes Mode 7 (EXPE = 1) Mode 7 (EXPE = 0) Advanced mode Advanced mode External mode with on-chip ROM enabled Single-chip mode H'000000 H'000000...
Page 95: Section 4 Exception Handling
Section 4 Exception Handling Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trace, interrupt, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority.
Page 96: Exception Sources And Exception Vector Table
Exception Sources and Exception Vector Table Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. Since the usable modes differ depending on the product, for details on each product, refer to section 3, MCU Operating Modes. Table 4.2 Exception HandlingVector Table Vector Address*...
Page 97: Reset
Notes: 1. Lower 16 bits of the address. 2. Not available in this LSI. 3. Not available in this LSI. Becomes reserved for system use. 4. For details on internal interrupt vectors, see section 5.5, Interrupt Exception Handling Vector Table. Reset A reset has the highest exception priority.
Page 98: Interrupts After Reset
Prefetch of first Internal Vector fetch program instruction processing φ Internal address bus Internal read signal Internal write High signal Internal data (1)(3) Reset exception-handling vector address (when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception-handling vector address) Start address ((5)=(2)(4)) First program instruction Figure 4.1 Reset Sequence...
Page 99: Traces
Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details on interrupt control modes, see section 5, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction.
Page 100: Trap Instruction
Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The trap instruction exception handling is as follows: 1. The values in the program counter (PC), condition code register (CCR), and extended register (EXR) are saved in the stack.
Page 101: Stack Status After Exception Handling
Stack Status after Exception Handling Figure 4.2 shows the stack after completion of trap instruction exception handling and interrupt exception handling. (a) Normal Modes Reserved* CCR* CCR* PC (16 bits) PC (16 bits) Interrupt control mode 0 Interrupt control mode 2 (b) Advanced Modes Reserved* PC (24 bits)
Page 102: Usage Note
Usage Note When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by word size or longword size and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers: PUSH.W (or MOV.W Rn, @-SP) PUSH.L...
Page 103: Section 5 Interrupt Controller
Section 5 Interrupt Controller Features • Two interrupt control modes Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the interrupt control register (INTCR). • Priorities settable with IPR An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority levels can be set for each module for all interrupts except NMI.
Page 104: Figure 5.1 Block Diagram Of Interrupt Controller
A block diagram of the interrupt controller is shown in figure 5.1. INTM1, INTM0 INTCR NMIEG NMI input NMI input unit Interrupt request IRQ input unit IRQ input Vector number Priority ISCR determination Internal interrupt sources I2 to I0 WOVI to IICI3 Interrupt controller [Legend]...
Page 105: Input/Output Pins
Input/Output Pins Table 5.1 shows the pin configuration of the interrupt controller. Table 5.1 Pin Configuration Name Function Input Nonmaskable external interrupt Rising or falling edge can be selected. IRQ7 to IRQ0 Input Maskable external interrupts Rising, falling, or both edges, or level sensing, can be selected.
Page 106: Interrupt Control Register (Intcr)
5.3.1 Interrupt Control Register (INTCR) INTCR selects the interrupt control mode, and the detected edge for NMI. Bit Name Initial Value Description  R/(W) Reserved R/(W)  The initial value should not be changed. INTM1 Interrupt Control Select Mode 1 and 0 INTM0 These bits select either of two interrupt control modes for the interrupt controller.
Page 107: Interrupt Priority Registers A To K (Ipra To Iprk)
5.3.2 Interrupt Priority Registers A to K (IPRA to IPRK) IPR are eleven 16-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts other than NMI. The correspondence between interrupt sources and IPR settings is shown in table 5.2. Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits 14 to 12, 10 to 8, 6 to 4, and 2 to 0 sets the priority of the corresponding interrupt.
Page 108 Bit Name Initial Value R/W Description IPR6 Sets the priority of the corresponding interrupt source. IPR5 000: Priority level 0 (Lowest) IPR4 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (Highest) ...
Page 109: Irq Enable Register (Ier)
5.3.3 IRQ Enable Register (IER) IER controls enabling and disabling of interrupt requests IRQ7 to IRQ0. Bit Name Initial Value R/W Description IRQ7E IRQ7 Enable The IRQ7 interrupt request is enabled when this bit is IRQ6E IRQ6 Enable The IRQ6 interrupt request is enabled when this bit is IRQ5E IRQ5 Enable The IRQ5 interrupt request is enabled when this bit is...
Page 110: Irq Sense Control Registers (Iscr)
5.3.4 IRQ Sense Control Registers (ISCR) ISCR select the source that generates an interrupt request at pins IRQ7 to IRQ0. Bit Name Initial Value R/W Description IRQ7SCB IRQ7 Sense Control B IRQ7SCA IRQ7 Sense Control A 00: Interrupt request generated at IRQ7 input low level 01: Interrupt request generated at falling edge of IRQ7 input...
Page 111 Bit Name Initial Value R/W Description IRQ4SCB IRQ4 Sense Control B IRQ4SCA IRQ4 Sense Control A 00: Interrupt request generated at IRQ4 input low level 01: Interrupt request generated at falling edge of IRQ4 input 10: Interrupt request generated at rising edge of IRQ4 input 11: Interrupt request generated at both falling and rising edges of IRQ4 input...
Page 112: Irq Status Register (Isr)
Bit Name Initial Value R/W Description IRQ1SCB IRQ1 Sense Control B IRQ1SCA IRQ1 Sense Control A 00: Interrupt request generated at IRQ1 input low level 01: Interrupt request generated at falling edge of IRQ1 input 10: Interrupt request generated at rising edge of IRQ1 input 11: Interrupt request generated at both falling and rising edges of IRQ1 input...
Page 113: Software Standby Release Irq Enable Register (Ssier)
5.3.6 Software Standby Release IRQ Enable Register (SSIER) SSIER selects the IRQ pins used to recover from the software standby state. Bit Name Initial Value R/W Description SSI7 Software Standby Release IRQ Setting These bits select the IRQn pins used to recover from SSI6 the software standby state.
Page 114: Internal Interrupts
Detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been set for input or output. However, when a pin is used as an external interrupt input pin, do not clear the corresponding DDR to 0 and use the pin as an I/O pin for another function. A block diagram of interrupts IRQ7 to IRQ0 is shown in figure 5.2.
Page 115: Table 5.2 Interrupt Sources, Vector Addresses, And Interrupt Priorities
Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities Origin of Vector Address* Interrupt Interrupt Vector Source Source Number Advanced Mode Priority  External H'001C High IRQ0 H'0040 IPRA14 to IPRA12 IRQ1 H'0044 IPRA10 to IPRA8 IRQ2 H'0048 IPRA6 to IPRA4 IRQ3 H'004C IPRA2 to IPRA0...
Page 116 Origin of Vector Address* Interrupt Interrupt Vector Source Source Number Advanced Mode Priority H’00B8 IRPE2 to IRPE0 High TPU_0 TGI0A H’00BC IPRF14 to IPRF12 TGI0B H'00C0 TGI0C H'00C4 TCI0D H'00C8 TCI0V H'00CC TPU_1 TGI1A H'00D0 IPRF10 to IPRF8 TGI1B H'00D4 TCI1V H'00D8 TCI1U...
Page 117 Origin of Vector Address* Interrupt Interrupt Vector Source Source Number Advanced Mode Priority TMRY_0 CMIAY0 H'0134 IPRG2 to IPRG0 High CMIBY0 H'0138 OVIY0 H'013C TMRX_1 CMIAX1 H'0140 IPRH14 to IPRH12 CMIBX1 H'0144 OVIX1 H'0148 ICIX1 H'014C FRT_1 ICIA1 H'0150 IPRH10 to IPRH8 ICIB1 H'0154 ICIC1...
Page 118 Origin of Vector Address* Interrupt Interrupt Vector Source Source Number Advanced Mode Priority SCI_1 ERI1 H'01A8 IPRI2 to IPRI0 High RXI1 H'01AC TXI1 H'01B0 TEI1 H'01B4 SCI_2 ERI2 H'01B8 IPRJ14 to IPRJ12 RXI2 H'01BC TXI2 H'01C0 TEI2 H'01C4 SCI_3 ERI3 H'01C8 IPRJ10 to IPRJ8 RXI3...
Page 119: Interrupt Control Modes And Interrupt Operation
Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is selected by INTCR. Table 5.3 shows the differences between interrupt control mode 0 and interrupt control mode 2.
Page 120: Figure 5.3 Flowchart Of Procedure Up To Interrupt Acceptance In Interrupt Control Mode 0
Program execution status Interrupt generated? I = 0 Hold pending IRQ0 IRQ1 IICI3 Save PC and CCR I ← 1 Read vector address Branch to interrupt handling routine Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 Rev.
Page 121: Interrupt Control Mode 2
5.6.2 Interrupt Control Mode 2 In interrupt control mode 2, mask control is done in eight levels for interrupt requests except for NMI by comparing the EXR interrupt mask level (I2 to I0 bits) in the CPU and the IPR setting. Figure 5.4 shows a flowchart of the interrupt acceptance operation in this case.
Page 122: Figure 5.4 Flowchart Of Procedure Up To Interrupt Acceptance In Interrupt Control Mode 2
Program execution status Interrupt generated? Level 7 interrupt? Level 6 interrupt? Mask level 6 or below? Level 1 interrupt? Mask level 5 or below? Mask level 0? Hold Save PC, CCR, and EXR pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance...
Page 123: Interrupt Exception Handling Sequence
5.6.3 Interrupt Exception Handling Sequence Figure 5.5 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. Rev.
Page 124: Figure 5.5 Interrupt Exception Handling
Figure 5.5 Interrupt Exception Handling Rev. 1.00, 09/03, page 86 of 704...
Page 125: Interrupt Response Times
5.6.4 Interrupt Response Times Table 5.4 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.4 are explained in table 5.5. This LSI is capable of fast word transfer to on-chip memory, and have the program area in on-chip ROM and the stack area in on-chip RAM, enabling high-speed processing.
Page 126: Usage Notes
Usage Notes 5.7.1 Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared to mask interrupts, the masking becomes effective after execution of the instruction. When an interrupt enable bit is cleared by an instruction such as BCLR or MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction.
Page 127: Instructions That Disable Interrupts
5.7.2 Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends.
Page 128: Note On Irq Status Register (Isr)
5.7.6 Note on IRQ Status Register (ISR) Since IRQnF flags may be set to 1 depending on the pin states after a reset, be sure to read from ISR after a reset and then write 0 to clear the IRQnF flags. Rev.
Page 129: Section 6 Bus Controller (Bsc)
Section 6 Bus Controller (BSC) This LSI has an on-chip bus controller (BSC) that manages the bus width and the number of access states of the external address space. Features • Extended modes Two modes for external extension Normal extended mode: Normal extension (when the ADMXE bit in BCR is 0) Address-data multiplex extended mode: Multiplex extension (when the ADMXE bit in BCR is •...
Page 130: Figure 6.1 Block Diagram Of Bus Controller
Multiplex Extension: The address output pins and data input/output pins are multiplex pins • Minimization of number of pins It is possible to minimize the number of pins necessary for expansion by multiplexing the address output pins and data input/output pins. •...
Page 131: Input/Output Pins
Input/Output Pins Table 6.1 summarizes the pin configuration of the bus controller. Table 6.1 Pin Configuration Symbol Function Output Strobe signal indicating that address output on address bus is enabled, during normal expansion Output Chip select signal indicating that area 1 is accessed Output Chip select signal indicating that area 2 is accessed Output...
Page 132: Register Descriptions
Register Descriptions Registers related to the bus controller are as follows. • Bus control register (BCR) • Basic area/area 1 control register (BCRA1) • Area 2 control register (BCRA2) • Area 3 control register (BCRA3) 6.3.1 Bus Control Register (BCR) BCR is used to specify the external extended selection, inversion control of CS1 to CS3, AS, and AH pins, as well as idle cycle insertion.
Page 133: Area Control Register (Bcra)
Initial Bit Name Value Description ADMXE Address and Data Multiplex Bus Interface Enable Selects the type of external extended bus interface. 0: Normal extended bus interface 1: Address and data multiplex extended bus interface 6.3.2 Area Control Register (BCRA) BCRA designates the access mode in area 1 to area 3. The basic area indicates the setting of area Initial Bit Name Value...
Page 134 Initial Bit Name Value Description Multiplex Extended Address Wait Selects the number of address cycle program waits in area n. Normal extension (ADMXE = 0): Ignored Multiplex extension (ADMXE = 1): 0: Program wait is not inserted 1: 1-state program wait is inserted into the address cycle WMSn1 Area n Wait Mode Select 1, 0 WMSn0...
Page 135: Bus Control
Bus Control 6.4.1 Bus Specifications The external address space bus specifications consist of three elements: bus width, number of access states, and the number of wait modes and program wait states. The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller.
Page 136: Table 6.3 Bus Specifications For Normal Extended Bus Interface
Table 6.3 Bus Specifications for Normal Extended Bus Interface Number of Number of ASTn WMSn1 WMSn0 WCn1 WCn0 Access Program States Wait States       [Legend] n = 1 to 3 *: Don’t care. Multiplex Extended Mode: The bus access is used as both the address bus and the data bus, but not simultaneously.
Page 137: Table 6.4 Address Range And External Address Area (Multiplex Extended Mode)
The external extended wait function is effective when the low-speed device is connected to the external address area. For details on multiplex extended address range, external address area, as well as bus interface specifications, refer to tables 6.4 to 6.6. Table 6.4 Address Range and External Address Area (Multiplex Extended Mode) Address Range...
Page 138: External Address Area
6.4.2 External Address Area The initial condition of the external address space is normal extended 3-state access space. The space outside the on-chip ROM, on-chip RAM, internal I/O register, and their reserved areas are available as the external address spaces. When the RAME bit in SYSCR is set to 1, the on-chip RAM and its reserved area are enabled.
Page 139: Address Strobe/Hold Signal
6.4.4 Address Strobe/Hold Signal In normal extended mode, the address above the bus address is enabled, which is indicated by the output strobe signal (AS). In multiplex extended mode, the hold signal (AH) which indicates the address fetch timing, is output. Output polarity of the AS/ AH signals can be controlled by the PNCASH bit in BCR.
Page 140: Bus Interface
Bus Interface The normal extended bus interface enables direct connection between the ROM and SRAM. For details on the basic area and areas 1 to 3 bus specification selection, refer to tables 6.2 and 6.3. For multiplex extended bus interface, only products compatible with this bus system can be directly connected.
Page 141: Figure 6.4 Access Sizes And Data Alignment Control (16-Bit Access Space)
16-Bit Access Space: Figure 6.4 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D15 to D8/AD15 to AD8) and lower data bus (D7 to D0/AD7 to AD0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word. A longword access is executed as two word accesses.
Page 142: Valid Strobes
6.5.2 Valid Strobes Table 6.7 shows the data buses used and valid strobes for each access space. In a read, the RD signal is valid for both the upper and lower halves of the data bus. In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half.
Page 143: Basic Operation Timing In Normal Extended Mode
6.5.3 Basic Operation Timing in Normal Extended Mode 8-Bit, 2-State Access Space: Figure 6.5 shows the bus timing for an 8-bit, 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. Wait states cannot be inserted. Bus cycle Address bus D15 to D8...
Page 144: Figure 6.6 Bus Timing For 8-Bit, 3-State Access Space
8-Bit, 3-State Access Space: Figure 6.6 shows the bus timing for an 8-bit, 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. Wait states can be inserted. Bus cycle Address bus D15 to D8...
Page 145: Figure 6.7 Bus Timing For 16-Bit, 2-State Access Space (Even Byte Access)
16-Bit, 2-State Access Space: Figures 6.7 to 6.9 show bus timings for a 16-bit, 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for even addresses, and the lower half (D7 to D0) for odd addresses.
Page 146: Figure 6.8 Bus Timing For 16-Bit, 2-State Access Space (Odd Byte Access)
Bus cycle Address bus D15 to D8 Invalid Read D7 to D0 Valid High Write D15 to D8 Undefined D7 to D0 Valid Note: n = 1 to 3 Figure 6.8 Bus Timing for 16-Bit, 2-State Access Space (Odd Byte Access) Rev.
Page 147: Figure 6.9 Bus Timing For 16-Bit, 2-State Access Space (Word Access)
Bus cycle Address bus D15 to D8 Valid Read D7 to D0 Valid Write D15 to D8 Valid D7 to D0 Valid Note: n = 1 to 3 Figure 6.9 Bus Timing for 16-Bit, 2-State Access Space (Word Access) Rev. 1.00, 09/03, page 109 of 704...
Page 148: Figure 6.10 Bus Timing For 16-Bit, 3-State Access Space (Even Byte Access)
16-Bit, 3-State Access Space: Figures 6.10 to 6.12 show bus timings for a 16-bit, 3-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for even addresses, and the lower half (D7 to D0) for odd addresses.
Page 149: Figure 6.11 Bus Timing For 16-Bit, 3-State Access Space (Odd Byte Access)
Bus cycle Address bus D15 to D8 Read Invalid D7 to D0 Valid High Write Undefined D15 to D8 D7 to D0 Valid Note: n = 1 to 3 Figure 6.11 Bus Timing for 16-Bit, 3-State Access Space (Odd Byte Access) Rev.
Page 150: Figure 6.12 Bus Timing For 16-Bit, 3-State Access Space (Word Access)
Bus cycle Address bus D15 to D8 Valid Read D7 to D0 Valid Write D15 to D8 Valid D7 to D0 Valid Note: n = 1 to 3 Figure 6.12 Bus Timing for 16-Bit, 3-State Access Space (Word Access) Rev. 1.00, 09/03, page 112 of 704...
Page 151: Basic Operation Timing In Multiplex Extended Mode
6.5.4 Basic Operation Timing in Multiplex Extended Mode 8-Bit, 2-State Data Access Space: Figures 6.13 and 6.14 show the bus timing for an 8-bit, 2-state access space. When an 8-bit access space is accessed, the upper half (AD15 to AD8) of the address bus and the data bus is used. Wait states cannot be inserted.
Page 152: Figure 6.14 Bus Timing For 8-Bit, 2-State Data Access Space (Without Address Wait)
Read Cycle Write Cycle Address Data Address Data AD15 to AD8 Address Address Data Data Note: n = 1 to 3 Figure 6.14 Bus Timing for 8-Bit, 2-State Data Access Space (Without Address Wait) Rev. 1.00, 09/03, page 114 of 704...
Page 153: Figure 6.15 Bus Timing For 8-Bit, 3-State Data Access Space (With Address Wait)
8-Bit, 3-State Data Access Space: Figure 6.15 shows the bus timing for an 8-bit, 3-state access space. When an 8-bit access space is accessed, the upper half (AD15 to AD8) of the address bus and the data bus are used. Wait states can be inserted.
Page 154: Figure 6.16 Bus Timing For 16-Bit, 2-State Data Access Space (1) (Even Byte Access, With Address Wait)
16-Bit, 2-State Data Access Space: Figures 6.16 to 6.21 show bus timings for a 16-bit, 2-state access space. When a 16-bit access space is accessed, the address bus uses all buses (AD15 to AD0), the upper half (AD15 to AD8) of the data bus is used for even addresses, and the lower half (AD7 to AD0) for odd addresses.
Page 155: Figure 6.17 Bus Timing For 16-Bit, 2-State Data Access Space (2) (Even Byte Access, Without Address Wait)
Read Cycle Write Cycle Address Data Address Data AD15 to AD8 Address Address Data Data AD7 to AD0 Address Address Note: n = 1 to 3 Figure 6.17 Bus Timing for 16-Bit, 2-State Data Access Space (2) (Even Byte Access, without Address Wait) Rev.
Page 156: Figure 6.18 Bus Timing For 16-Bit, 2-State Access Space (3) (Odd Byte Access, With Address Wait)
Read Cycle Write Cycle Address Data Address Data AD15 to AD8 Address Address AD7 to AD0 Address Data Address Data Note: n = 1 to 3 Figure 6.18 Bus Timing for 16-Bit, 2-State Access Space (3) (Odd Byte Access, with Address Wait) Rev.
Page 157: Figure 6.19 Bus Timing For 16-Bit, 2-State Data Access Space (4) (Odd Byte Access, Without Address Wait)
Read Cycle Write Cycle Address Data Address Data AD15 to AD8 Address Address Address Address Data Data AD7 to AD0 Note: n = 1 to 3 Figure 6.19 Bus Timing for 16-Bit, 2-State Data Access Space (4) (Odd Byte Access, without Address Wait) Rev.
Page 158: Figure 6.20 Bus Timing For 16-Bit, 2-State Data Access Space (5) (Word Access, With Address Wait)
Read Cycle Write Cycle Address Data Address Data AD15 to AD8 Data Address Address Data AD7 to AD0 Data Address Address Data Note: n = 1 to 3 Figure 6.20 Bus Timing for 16-Bit, 2-State Data Access Space (5) (Word Access, with Address Wait) Rev.
Page 159: Figure 6.21 Bus Timing For 16-Bit, 2-State Data Access Space (6) (Word Access, Without Address Wait)
Read Cycle Write Cycle Address Data Address Data Address Address AD15 to AD8 Data Data Address AD7 to AD0 Address Data Data Note: n = 1 to 3 Figure 6.21 Bus Timing for 16-Bit, 2-State Data Access Space (6) (Word Access, without Address Wait) Rev.
Page 160: Figure 6.22 Bus Timing For 16-Bit, 3-State Data Access Space (1) (Even Byte Access, With Address Wait)
16-Bit, 3-State Data Access Space: Figures 6.22 to 6.24 show bus timings for a 16-bit, 3-state access space. When a 16-bit access space is accessed, the address bus uses all buses (AD15 to AD0), the upper half (AD15 to AD8) of the data bus is used for even addresses, and the lower half (AD7 to AD0) for odd addresses.
Page 161: Figure 6.23 Bus Timing For 16-Bit, 3-State Data Access Space
Read Cycle Write Cycle Data Address Address Data AD15 to AD8 Address Address AD7 to AD0 Data Address Address Data Note: n = 1 to 3 Figure 6.23 Bus Timing for 16-Bit, 3-State Data Access Space (2) (Odd Byte Access, with Address Wait) Rev.
Page 162: Figure 6.24 Bus Timing For 16-Bit, 3-State Data Access Space
Read Cycle Write Cycle Data Address Address Data AD15 to AD8 Data Address Address Data AD7 to AD0 Data Address Address Data Note: n = 1 to 3 Figure 6.24 Bus Timing for 16-Bit, 3-State Data Access Space (3) (Word Access, with Address Wait) Rev.
Page 163: Wait Control
6.5.5 Wait Control When accessing the external address space, this LSI can extend the bus cycle by inserting the wait states (T ). Ways of inserting wait states: Program wait insertion, pin wait insertion using the WAIT pin, and the combination of program wait and the WAIT pin. In Normal Extended Mode: 1.
Page 164: Figure 6.25 Example Of Wait State Insertion Timing (Normal Extended Pin Wait Mode)
By program wait Address bus Read Data bus Read data Write Data bus Write data Notes: 1. Downward arrows indicate the timing of pin sampling. 2. n = 1 to 3 Figure 6.25 Example of Wait State Insertion Timing (Normal Extended Pin Wait Mode) In Multiplex Extended Mode: 1.
Page 165: Figure 6.26 Example Of Wait State Insertion Timing (Multiplex Extended Mode)
2. Pin Wait Mode When accessing the external address space, a specified number of wait states T can be state of data state. If the WAIT pin is low at the falling inserted between the T state and T state is inserted. If the WAIT pin is held low, edge of φ...
Page 166: Idle Cycle
Idle Cycle When this LSI accesses the external address space, it can insert a 1-state idle cycle (T ) between bus cycles when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible, for example, to avoid data collisions between ROM with a long output floating time, and high-speed memory and I/O interfaces.
Page 167: Table 6.8 Pin States In Idle Cycle
Table 6.8 Pin States in Idle Cycle Pins Pin State A15 to A0 Contents of immediately following bus cycle D15 to D0 High impedance AD15 to AD0 High impedance AS/AH High when PNCASH = 0. Low when PNCASH = 1. High when PNCCSn = 0.
Page 168 Rev. 1.00, 09/03, page 130 of 704...
Page 169: Section 7 I/O Ports
Section 7 I/O Ports Table 7.1 is a summary of the port functions. The pins of each port also function as input/output pins of peripheral modules and interrupt input pins. Each input/output port includes a data direction register (DDR) that controls input/output, a data register (DR) that stores output data, and a port register (PORT) that reads a pin state.
Page 170: Table 7.1 Port Functions (1)
Table 7.1 Port Functions (1) Extended Mode (EXPE = 1) Single-Chip Mode Port Description (EXPE = 0) I/O Status Normal Multiplex Port 0 General input P07/AN15/ExIRQ7 port also P06/AN14/ExIRQ6 functioning as P05/AN13/ExIRQ5 an A/D converter P04/AN12/ExIRQ4 analog input P03/AN11 and interrupt P02/AN10 input.
Page 171: Table 7.1 Port Functions (2)
Table 7.1 Port Functions (2) Extended Mode(EXPE = 1) Single-Chip Mode (EXPE = 0) Port Description I/O Status Normal Multiplex Port 3 General I/O On-chip port also input pull-up functioning as a bidirectional data bus and interrupt input. P33/ExIRQ3 P32/ExIRQ2 P31/ExIRQ1 P30/ExIRQ0 Port 4...
Page 172: Table 7.1 Port Functions (3)
Table 7.1 Port Functions (3) Extended Mode (EXPE = 1) Single-Chip Mode Port Description (EXPE = 0) I/O Status Normal Multiplex Port 6 General I/O port P67/RxD2* On-chip also functioning input pull-up P66/TxD2* as a P65/SCK2* bidirectional Open-drain data bus, P64/FTCI_1* output FRT_1...
Page 173: Table 7.1 Port Functions (4)
Table 7.1 Port Functions (4) Extended Mode (EXPE = 1) Single-Chip Mode Port Description (EXPE = 0) I/O Status Normal Multiplex Port 8 General I/O P87/ADTRG/ExTIOCB0 NMOS push- port also pull output P86/ExTIOCA0 functioning as (P80 to P83) P85/PWX1 an A/D converter P84/PWX0 external...
Page 174: Table 7.1 Port Functions (5)
Table 7.1 Port Functions (5) Extended Mode (EXPE = 1) Single-Chip Mode Port Description (EXPE = 0) I/O Status Normal Multiplex Port A General I/O port PA7/CS3/ExTIOCA1 PA7/ExTIOCA1 also functioning PA6/FTCI_0/HFBACKI as a bus control PA5/FTIB_0/VFBACKI output, FRT_0 input/output, PA4/FTIC_0/CLAMPO TMX_0, TMY_0, PA3/FTOB_0/CBLANK and TM0_0...
Page 175: Port 0
Port 0 Port 0 is an 8-bit input port. Port 0 pins also function as A/D converter analog input pins and EXIRQ input pins. Port 0 has the following register. • Port 0 register (PORT0) 7.1.1 Port 0 Register (PORT0) PORT0 is an 8-bit read-only register, that reflects the pin state in port 0.
Page 176 • P07/AN15/ExIRQ7 P07 input pin function AN15 input pin/ExIRQ7 input pin* * When the IRQ7S bit in PTCNT1 is set to 1, it functions as the ExIRQ7 input. Note: • P06/AN14/ExIRQ6 P06 input pin function AN14 input pin/ExIRQ6 input pin* * When the IRQ6S bit in PTCNT1 is set to 1, it functions as the ExIRQ6 input.
Page 177: Port 1
Port 1 Port 1 is an 8-bit I/O port. Port 1 pins also function as address bus pins, address/data multiplex bus pins, and PWM output pins. Pin functions change according to the operating mode. Port 1 has the following registers. •...
Page 178: Port 1 Data Register (P1Dr)
7.2.2 Port 1 Data Register (P1DR) P1DR stores output data for port 1. Bit Name Initial Value Description P17DR P1DR stores output data for the port 1 pins that are used as the general output ports. P16DR P15DR P14DR P13DR P12DR P11DR P10DR...
Page 179: Port 1 Pull-Up Mos Control Register (P1Pcr)
7.2.4 Port 1 Pull-Up MOS Control Register (P1PCR) P1PCR controls the on or off state of input pull-up MOSs for port 1. Bit Name Initial Value Description • P17PCR In normal extended and single-chip modes When the pins are in the input states, the P16PCR corresponding input pull-up MOS is turned on P15PCR...
Page 180: Port 1 Input Pull-Up Mos States
• Single-Chip Mode (EXPE = 0) P1nDDR  PWnS   Pin function P1n input pin P1n output pin P1n output pin PWn output pin [Legend] n = 7 to 0 7.2.6 Port 1 Input Pull-Up MOS States Port 1 has an on-chip input pull-up MOS that can be controlled by software. This input pull-up MOS can be used regardless of the operating mode.
Page 181: Port 2
Port 2 Port 2 is an 8-bit I/O port. Port 2 pins also function as address bus pins, address/data multiplex bus pins, and TPU I/O pins. Pin functions change according to the operating mode. Port 2 has the following registers. •...
Page 182: Port 2 Data Register (P2Dr)
7.3.2 Port 2 Data Register (P2DR) P2DR stores output data for the port 2 pins. Bit Name Initial Value Description P27DR P2DR stores output data for the port 2 pins that are used as the general output ports. P26DR P25DR P24DR P23DR P22DR...
Page 183: Port 2 Pull-Up Mos Control Register (P2Pcr)
7.3.4 Port 2 Pull-Up MOS Control Register (P2PCR) P2PCR controls the on or off state of input pull-up MOSs for port 2. Bit Name Initial Value Description • P27PCR In normal extended and single-chip modes When the pins are in the input states, the P26PCR corresponding input pull-up MOS is turned on P25PCR...
Page 184 • Single-Chip Mode (EXPE = 0) TIOCB2/ TCLKDS  TPU channel Table below (2) Table below (1) 2 setting  P27DDR Pin function P27 input pin P27 output pin TIOCB2 output P27 input pin P27 output pin TIOCB2 input pin* TCLKD input pin* TPU channel 2 setting...
Page 185 • Single-Chip Mode (EXPE = 0) TIOCA2S  TPU channel Table below (2) Table below (1) 2 setting  P26DDR Pin function P26 input pin P26 output pin TIOCA2 output P26 input pin P26 output pin TIOCA2 input pin* TPU channel 2 setting MD3 to MD0 B'0000, B'01xx...
Page 186 • Extended Mode (EXPE = 1) Normal Extended Mode (ADMXE = 0) Multiplex Extended Mode (ADMXE = 1)  P25DDR Pin function P25 input pin A13 output pin AD13 I/O pin TIOCB1 input pin* TCLKC input pin* • Single-Chip Mode (EXPE = 0) TIOCB1/ TCLKCS ...
Page 187 • P24/TIOCA1/A12/AD12 When the TIOCA1S bit in PTCNT2 is cleared to 0, this pin can be used as the TIOCA1 pin. According to operating modes, the TPU channel 1 settings by the MD3 to MD0 bits in TMDR_1, the IOA3 to IOA0 bits in TIOR_1, and the CCLR1 and CCLR0 bits in TCR_1, and the combination of the TIOCA1S bit and the P24DDR bit, pin functions change as follows.
Page 188 • P23/TIOCD0/TCLKB/A11/AD11 When the TIOCD0/TCLKBS bit in PTCNT2 is cleared to 0, this pin can be used as the TIOCD0/TCLKB pin. According to operating modes, the TPU channel 0 settings by the MD3 to MD0 bits in TMDR_0, the IOD3 to IOD0 bits in TIORL_0, and the CCLR2 to CCLR0 bits in TCR_0, and the combination of the TPSC2 to TPSC0 bits in TCR_0 to TCR_2, the TIOCD0/TCLKBS bit, and the P23DDR bit, pin functions change as follows.
Page 189 [Legend] x: Don’t care Notes: 1. When TIOCD0/TCLKBS = 0, MD3 to MD0 = B'0000, and IOD3 to IOD0 = B'10xx, this pin functions as the TIOCD0 input pin. 2. When TIOCD0/TCLKBS = 0 and TPSC2 to TPSC0 in one of TCR_0 to TCR2 = B′101, this pin functions as the TCLKB input pin.
Page 190 TPU channel 0 setting MD3 to MD0 B'0000 B'001x B'0010 B'0011 IOC3 to IOC0 B'0000 B'0001 to B'0011 B'xx00 Other Other than B'xx00 than B'0100 B'0101 to B'0111 B'xx00 B'1xxx     CCLR2 to Other than B'101 CCLR0 B'101 ...
Page 191 TPU channel 0 setting MD3 to MD0 B'0000 B'0010 B'0011  IOB3 to IOB0 B'0000 B'0001 to B′0011 B'xx00 Other than B'xx00 B'0100 B'0101 to B′0111 B'1xxx     CCLR2 to Other than B'10 CCLR0 B'10   ...
Page 192: Port 2 Input Pull-Up Mos States
TPU channel 0 setting MD3 to MD0 B'0000 B'001x B'0010 B'0011 IOA3 to IOA0 B'0000 B'0001 to B'0011 B'xx00 Other than Other than B'xx00 B'xx00 B'0100 B'0101 to B'0111 B'1xxx     CCLR2 to Other than B'001 CCLR0 B'001 ...
Page 193: Port 3
Port 3 Port 3 is an 8-bit I/O port. Port 3 pins also function as bidirectional data bus and ExIRQ input pins. Port 3 functions change according to the operating mode. Port 3 has the following registers. • Port 3 data direction register (P3DDR) •...
Page 194: Port 3 Data Register (P3Dr)
7.4.2 Port 3 Data Register (P3DR) P3DR stores output data for the port 3 pins. Bit Name Initial Value Description P37DR P3DR stores output data for the port 3 pins that are used as the general output ports. P36DR P35DR P34DR P33DR P32DR...
Page 195: Port 3 Pull-Up Mos Control Register (P3Pcr)
7.4.4 Port 3 Pull-Up MOS Control Register (P3PCR) P3PCR controls the on or off state of input pull-up MOSs for port 3. Bit Name Initial Value Description • P37PCR In normal extended mode Operation is not affected. P36PCR • In multiplex extended mode P35PCR Operates as single-chip mode P34PCR...
Page 196 • P36/D14 The pin function is switched as shown below according to the operating mode and the P36DDR bit. Extended Mode (EXPE = 1) Normal Extended Mode Multiplex Extended Mode (ADMXE = 0) (ADMXE = 1) Single-Chip Mode (EXPE = 0) ...
Page 197 • P33/D11/ExIRQ3 When the IRQ3S bit in PTCNT1 is set to 1, this pin can be used as the ExIRQ3 pin. The pin function is switched as shown below according to the operating mode, the IRQ3S bit, and the P33DDR bit. Extended Mode (EXPE = 1) Normal Extended Mode...
Page 198 • P31/D9/ExIRQ1 When the IRQ1S bit in PTCNT1 is set to 1, this pin can be used as the ExIRQ1 pin. The pin function is switched as shown below according to the operating mode, the IRQ1S bit, and the P31DDR bit. Extended Mode (EXPE = 1) Normal Extended Mode...
Page 199: Port 3 Input Pull-Up Mos States
7.4.6 Port 3 Input Pull-Up MOS States Port 3 has an on-chip input pull-up MOS that can be controlled by software. This input pull-up MOS can be used in single-chip and multiplex extended modes. Table 7.4 summarizes the input pull-up MOS states. Table 7.4 Port 3 Input Pull-Up MOS States Hardware...
Page 200: Port 4
Port 4 Port 4 is an 8-bit I/O port. Port 4 pins also function as external interrupt pins, TMR0_0, TMR0_1, TMRX_0, TMRY_0, TMRX_1, TMRY_1, and FRT_1 input pins, and PWM output pins. Port 4 has the following registers. • Port 4 data direction register (P4DDR) •...
Page 201: Port 4 Data Register (P4Dr)
7.5.2 Port 4 Data Register (P4DR) P4DR stores output data for the port 4 pins. Bit Name Initial Value Description P47DR P4DR stores output data for the port 4 pins that are used as the general output ports. P46DR P45DR P44DR P43DR P42DR...
Page 202: Pin Functions
7.5.4 Pin Functions When the corresponding bit in PTCNT1 is cleared to 0, port 4 pins can be used as interrupt input pins (IRQ7 to IRQ0). When the corresponding bit in PTCNT0 is set to 1, port 4 pins can be used as PWM output pins (ExPW3 to ExPW0).
Page 203 P46DDR  PW2S   Pin function P46 input pin P46 output pin P46 output pin PW2 output pin TMIX_0 (TMCIX/TMRIX) input pin IRQ6 input pin* * When the IRQ6S bit in PTCNT1 is cleared to 0, this pin functions as the IRQ6 input pin. Note: •...
Page 204 P44DDR  PW0S   Pin function P44 input pin P44 output pin P44 output pin PW0 output pin TMIY_1 (TMCIY/TMRIY) input pin IRQ4 input pin* * When the IRQ4S bit in PTCNT1 is cleared to 0, this pin functions as the IRQ4 input pin. Note: •...
Page 205 • P41/IRQ1/FTIC_1 When the IRQ1S bit in PTCNT1 is cleared to 0, this pin can be used as an IRQ1 pin. The pin function is switched as shown below according to the combination of the IRQ1S bit and the P41DDR bit. When the ICICE bit in TIER of the FRT_1 is set to 1, this pin functions as an FTIC_1 input pin.
Page 206: Port 5
Port 5 Port 5 is an 8-bit I/O port. Port 5 pins also function as TMR0_1 and TMR1_1 output pins, SCI_0 and SCI_1 I/O pins, and PWM output pins. Port 5 has the following registers. • Port 5 data direction register (P5DDR) •...
Page 207: Port 5 Data Register (P5Dr)
7.6.2 Port 5 Data Register (P5DR) P5DR stores output data for the port 5 pins. Bit Name Initial Value Description P57DR P5DR stores output data for the port 5 pins that are used as the general output ports. P56DR P55DR P54DR P53DR P52DR...
Page 208: Pin Functions
7.6.4 Pin Functions When the corresponding bit in PTCNT0 is set to 1, port 5 pins can be used as PWM output pins (ExPW5 and ExPW4). The relationship between register setting values and pin functions is as follows. • P57/TMO1_1/ExPW5 When the PW5S bit in PTCNT0 is set to 1, this pin can be used as an ExPW5 pin.
Page 209 • P55/RxD1 The pin function is switched as shown below according to the combination of the RE bit in SCR of the SCI_1 and the P55DDR bit.  P55DDR Pin function P55 input pin P55 output pin RxD1 input pin •...
Page 210 • P51/TxD0 The pin function is switched as shown below according to the combination of the TE bit in SCR of the SCI_0 and the P51DDR bit.  P51DDR Pin function P51 input pin P51 output pin TxD0 output pin •...
Page 211: Port 6
Port 6 Port 6 is an 8-bit I/O port. Port 6 pins also function as bidirectional data bus, SCI_2 I/O pins, FRT_1 I/O pins, and TMRX_1 and TMRY_1 output pins. Port 6 functions change according to the operating mode. Port 6 has the following registers. •...
Page 212: Port 6 Data Register (P6Dr)
7.7.2 Port 6 Data Register (P6DR) P6DR stores output data for the port 6 pins. Bit Name Initial Value Description P67DR P6DR stores output data for the port 6 pins that are used as the general output ports. P66DR P65DR P64DR P63DR P62DR...
Page 213: Port 6 Pull-Up Mos Control Register (P6Pcr)
7.7.4 Port 6 Pull-Up MOS Control Register (P6PCR) P6PCR controls the on or off state of input pull-up MOSs for port 6. Bit Name Initial Value Description • P67PCR In normal extended mode (16-bit data bus) Operation is not affected. P66PCR •...
Page 214 Multiplex Extended Mode Normal Extended Mode (ADMXE = 0) (ADMXE = 1)  Bus width* 16-bit 8-bit  Single-chip operation Single-chip operation  P67DDR Pin function D7 I/O pin Note: * When the ABW3 to ABW1 bits in BCRA3 to BCRA1 are all set to 1, bus width is 8 bits, if any are cleared to 0, bus width is 16 bits.
Page 215 • P66/TxD2/D6 The pin function is switched as shown below according to the combination of the operating mode, the TE bit in SCR of the SCI_2, and the P66DDR bit. • Extended Mode (EXPE = 1) Multiplex Extended Mode Normal Extended Mode (ADMXE = 0) (ADMXE = 1) ...
Page 216 • Single-Chip Mode (EXPE = 0) CKE1    CKE0    P65DDR Pin function P65 input pin P65 output pin SCK2 output SCK2 output SCK2 input pin • P64/FTCI_1/D4 The pin function is switched as shown below according to the combination of the operating mode and the P64DDR bit.
Page 217 • P63/TMOY_1/D3 The pin function is switched as shown below according to the combination of the operating mode, the OS3 to OS0 bits in TCSR of the TMRY_1, and the P63DDR bit. • Extended Mode (EXPE = 1) Multiplex Extended Mode Normal Extended Mode (ADMXE = 0) (ADMXE = 1) ...
Page 218 • P61/FTOB_1/D1 The pin function is switched as shown below according to the combination of the operating mode, the OEB bit in TOCR of the FRT_1, and the P61DDR bit. • Extended Mode (EXPE = 1) Multiplex Extended Mode Normal Extended Mode (ADMXE = 0) (ADMXE = 1) ...
Page 219: Port 6 Input Pull-Up Mos States
7.7.7 Port 6 Input Pull-Up MOS States Port 6 has an on-chip input pull-up MOS that can be controlled by software. Table 7.5 summarizes the input pull-up MOS states. Table 7.5 Port 6 Input Pull-Up MOS States Hardware Standby Software Standby Reset Mode Mode...
Page 220: Pin Functions
7.8.2 Pin Functions Pin function relationships are listed below. • P77/AN7 P77 input pin function AN7 input pin • P76/AN6 P76 input pin function AN6 input pin • P75/AN5 P75 input pin function AN5 input pin • P74/AN4 P74 input pin function AN4 input pin •...
Page 221: Port 8
Port 8 Port 8 is an 8-bit I/O port. Port 8 pins also function as external trigger input pins for the A/D converter, PWMX output pins, SCI_3, SCI_4, IIC3_0, and IIC3_1 I/O pins, and TPU I/O pins. The output format for P80 to P83 which are general I/O ports is NMOS push-pull output. Port 8 has the following registers.
Page 222: Port 8 Data Register (P8Dr)
7.9.2 Port 8 Data Register (P8DR) P8DR stores output data for the port 8 pins. Bit Name Initial Value Description P87DR P8DR stores output data for the port 8 pins that are used as the general output ports. P86DR P85DR P84DR P83DR P82DR...
Page 223: Pin Functions
7.9.4 Pin Functions When the corresponding bit in PTCNT2 is set to 1, port 8 pins can be used as TPU I/O pins (ExTIOCB0 and ExTIOCA0). The relationship between register setting values and pin functions is as follows. • P87/ExTIOCB0/ADTRG When the TIOCB0S bit in PTCNT2 is set to 1, this pin can be used as an ExTIOCB0 pin.
Page 224 • P86/ExTIOCA0 When the TIOCA0S bit in PTCNT2 is set to 1, this pin can be used as an ExTIOCA0 pin. The pin function is switched as shown below according to the combination of the TPU channel 0 settings by the MD3 to MD0 bits in TMDR_0, the IOA3 to IOA0 bits in TIORH_0, and the CCLR2 to CCLR0 bits in TCR_0, the TIOCA0S bit, and the P86DDR bit.
Page 225 • P84/PWX0 The pin function is switched as shown below according to the combination of the OEA bit in DACR of the PWMX and the P84DDR bit.  P84DDR Pin function P84 input pin P84 output pin PWX0 output pin •...
Page 226 • P81/SDA0/RxD3 The pin function is switched as shown below according to the combination of the RE bit in SCR of the SCI_3, the ICE bit in ICCRA of the IIC3_0, and the P81DDR bit. When this pin is used as the P81 output pin, the output format is NMOS push-pull output. The output format for SDA0 is NMOS open-drain output, and direct bus drive is possible.
Page 227: Port 9
7.10 Port 9 Port 9 is an 8-bit I/O port. Port 9 pins also function as bus control I/O pins, system clock output pins, and TPU I/O pins. Port 9 functions change according to the operating mode. Port 9 has the following registers. •...
Page 228: Port 9 Data Register (P9Dr)
7.10.2 Port 9 Data Register (P9DR) P9DR stores output data for the port 9 pins. Bit Name Initial Value Description P97DR P9DR stores output data for the port 9 pins that are used as the general output ports. P96DR P95DR P94DR P93DR P92DR...
Page 229: Port Function Control Register (Pfcr)
7.10.4 Port Function Control Register (PFCR) PFCR controls the I/O port. Bit Name Initial Value Description 7 to 5  All 0 Reserved These bits are always read as 0. The write value should always be 0. CS3 Output Enable CS3E Selects to enable or disable the CS3 output.
Page 230: Pin Functions
7.10.5 Pin Functions When the corresponding bit in PTCNT2 is set to 1, port 9 pins can be used as TPU I/O pins (ExTIOCD0/ExTCLKB, ExTIOCB2/ExTCLKD, ExTIOCA2, and ExTIOCB1/ExTCLKC). The relationship between register setting values and pin functions is as follows. •...
Page 231 TPU channel 0 setting MD3 to MD0 B'0000 B'0010 B'0011  IOB3 to IOB0 B'0000 B'0001 to B'0011 B'xx00 Other than B'xx00 B'0100 B'0101 to B'0111 B'1xxx     CCLR2 to CCLR0 Other than B'110 B'110   ...
Page 232 • P94/HWR According to the operating mode and the setting of the P94DDR bit, the pin function is switched as shown below. Extended Mode (EXPE = 1) Single-Chip Mode (EXPE = 0)  P94DDR HWR output pin Pin function P94 input pin P94 output pin •...
Page 233 • Single-Chip Mode (EXPE = 0) TIOCB2/TCLKDS  TPU channel 2 setting Table below (2) Table below (1)  P92DDR Pin function P92 input P92 input pin P92 output pin ExTIOCB2 output output ExTIOCB2 input pin* ExTCLKD input pin* TPU channel 2 setting MD3 to MD0 B'0000, B'01xx B'0010...
Page 234 • Extended Mode (EXPE = 1) CS2E TIOCA2S Single-chip operation  TPU channel 2 setting Table below (2) Table below (1)    P91DDR CS2 output pin CS2 output pin CS2 output pin Pin function ExTIOCA2 input pin* • Single-Chip Mode (EXPE = 0) TIOCA2S ...
Page 235 • Extended Mode (EXPE = 1) LWROE TIOCB1/TCLKCS Single-chip operation  TPU channel 1 setting Table below (2) Table below (1)    P90DDR LWR output pin LWR output pin LWR output pin Pin function ExTIOCB1 input pin* ExTCLKC input pin* •...
Page 236: Port A
7.11 Port A Port A is an 8-bit I/O port. Port A pins also function as bus control output pins, SCI_3 and SCI_4 I/O pins, TMX_0, TMY_0, TM0_0, and PWM output pins, and FRT_0 and timer connection I/O pins. Port A has the following registers. For details on the port function control register, refer to section 7.10.4, Port Function Control Register (PFCR).
Page 237: Port A Data Register (Padr)
7.11.2 Port A Data Register (PADR) PADR stores output data for the port A pins. Bit Name Initial Value Description PA7DR PADR stores output data for the port A pins that are used as the general output ports. PA6DR PA5DR PA4DR PA3DR PA2DR...
Page 238: Pin Functions
7.11.4 Pin Functions When the corresponding bit in PTCNT2 is set to 1, port A pins can be used as TPU I/O pins (ExTIOCA1 and ExTIOCC0/ExTCLKA). The relationship between register setting values and pin functions is as follows. • PA7/CS3/ExTIOCA1 When the TIOCA1S bit in PTCNT2 is set to 1, this pin can be used as the ExTIOCA1 pin.
Page 239 TPU channel 1 setting MD3 to MD0 B'0000, B'01xx B'001x B'0010 B'0011 IOA3 to IOA0 B'0000 B'0001 to B'0011 B'xx00 Other than Other than B'xx00 B'xx00 B'0100 B'0101 to B'0111 B'1xxx     CCLR1, CCLR0 Other than B'01 B'01 ...
Page 240 • PA4/FTIC_0/CLAMPO According to the combination of the CLOE bit in TCONRO of the timer connection_0 and the PA4DDR bit, the pin function is switched as shown below. When the ICICE bit in TIER of the FRT_0 is set to 1, this pin functions as the FTIC_0 input pin.
Page 241 TPU channel 0 setting MD3 to MD0 B'0000 B'001x B'0010 B'0011 IOA3 to B'0000 B'0001 to B'0011 B'xx00 Other than Other than B'xx00 IOA0 B'xx00 B'0100 B'0101 to B'0111 B'1xxx     CCLR2 to Other than B'101 CCLR0 B'101 ...
Page 242 • PA0/TMOX_0/ExPW6/SCK3 When the PW6S bit in PTCNT0 is set to 1, this pin can be used as the ExPW6 pin. According to the combination of the C/A bit in SMR of the SCI_3, the CKE0 and CKE1 bits in SCR, the OS3 to OS0 bits in TCSR of the TMRX_0, the OE6 bit in PWOER of the PWM, the PW6S bit, and the PA0DDR bit, the pin function is switched as shown below.
Page 243: Port B
7.12 Port B Port B is an 8-bit I/O port. Port B pins also function as TMR1_1 input pins, TMR1_0 output pins, FRT_1 and timer connection_0 I/O pins, and timer connection_1 input pins. Port B has the following registers. • Port B data direction register (PBDDR) •...
Page 244: Port B Data Register (Pbdr)
7.12.2 Port B Data Register (PBDR) PBDR stores output data for the port B pins. Bit Name Initial Value Description PB7DR PBDR stores output data for the port B pins that are used as the general output ports. PB6DR PB5DR PB4DR PB3DR PB2DR...
Page 245: Pin Functions
7.12.4 Pin Functions The relationship between register setting values and pin functions is as follows. • PB7/TMI1_0/HSYNCI_0 According to the setting of the PB7DDR bit, the pin function is switched as shown below. When the external clock is selected by the CKS2 to CKS0 bits in TCR of the TMR1_0, this pin functions as the TMCI1_0 input pin.
Page 246 • PB4/TMI1_1/HSYNCI_1 According to the setting of the PB4DDR bit, the pin function is switched as shown below. When the external clock is selected by the CKS2 to CKS0 bits in TCR of the TMR1_1, this pin functions as the TMCI1_1 input pin. When the CCLR1 and CCLR0 bits in TCR of the TMR1_1 are all set to 1, this pin functions as the TMRI1_1 input pin.
Page 247 • PB1/TMO1_0/HSYNCO According to the combination of the HOE bit in TCONRO of the timer connection_0, the OS3 to OS0 bits in TCSR of the TMR1_0, and the PB1DDR bit, the pin function is switched as shown below.  OS3 to OS0 All 0 At least one bit is set to 1...
Page 248: Port C
7.13 Port C Port C is an 8-bit I/O port. Port C pins also function as IIC3_2 and IIC3_3 I/O pins and on-chip emulator I/O pins. The output format for PC0 to PC3 which are general I/O ports is NMOS push- pull output.
Page 249: Port C Register (Portc)
7.13.3 Port C Register (PORTC) PORTC reflects the pin state in port C and cannot be modified. Bit Name Initial Value Description * These bits are always read as pin states. * * * * When this register is read, the bit that is set in PCDDR is read as the value of PCDR.
Page 250 • PC4/ETMS Pin function PC4 input pin Note: When the on-chip emulator is used, this pin functions as the ETMS input pin. When no signal is input, this pin is fixed to 1 by the internal pull-up. • PC3/SDA3 The pin function is switched as shown below according to the combination of the ICE bit in ICCRA of the IIC3_3 and the PC3DDR bit.
Page 251 • PC0/SCL2 The pin function is switched as shown below according to the combination of the ICE bit in ICCRA of the IIC3_2 and the PC0DDR bit. When this pin is used as the PC0 output pin, the output format is NMOS push-pull output. The output format for SCL2 is NMOS open-drain output, and direct bus drive is possible.
Page 252: Change Of Peripheral Function Pins
7.14 Change of Peripheral Function Pins I/O ports that also function as peripheral modules, such as the 8-bit PWM timer output, external interrupts, and TPU I/O, and, can be changed. They are changed according to the setting of PTCNT0 to PTCNT2. The pin name of the peripheral function is indicated by adding ‘Ex’ at the head of the original pin name.
Page 253: Port Control Register 1 (Ptcnt1)
7.14.2 Port Control Register 1 (PTCNT1) PTCNT1 selects ports that also function as IRQ7 to IRQ0 input pins. Bit Name Initial Value Description Selects the IRQ7 input pin. IRQ7S 0: P47/IRQ7 is selected 1: P07/ExIRQ7 is selected Selects the IRQ6 input pin. IRQ6S 0: P46/IRQ6 is selected 1: P06/ExIRQ6 is selected...
Page 254: Port Control Register 2 (Ptcnt2)
7.14.3 Port Control Register 2 (PTCNT2) PTCNT2 selects ports that also function as TPU I/O pins. Bit Name Initial Value Description TIOCB2/ Selects the TIOCB2/TCLKD I/O pin for the TPU. TCLKDS 0: P27/TIOCB2/TCLKD is selected 1: P92/ExTIOCB2/ExTCLKD is selected TIOCA2S Selects the TIOCA2 I/O pin for the TPU.
Page 255: Section 8 8-Bit Pwm Timer (Pwm)
Section 8 8-Bit PWM Timer (PWM) This LSI has an on-chip pulse width modulation (PWM) timer with eight outputs. Eight output waveforms are generated from a common timebase, enabling PWM output with a high carrier frequency to be produced using pulse division. Features •...
Page 256: Input/Output Pin
Input/Output Pin Table 8.1 shows the PWM output pin. Table 8.1 Pin Configuration Name Symbol Function PWM output pins 7 to 0 PW7 to PW0 Output PWM timer pulse output 7 to 0 Register Descriptions The PWM has the following registers. •...
Page 257: Pwm Register Select (Pwsl)
8.3.1 PWM Register Select (PWSL) PWSL selects the input clock and the PWM data register. Bit Name Initial Value Description PWCKE PWM Clock Enable PWCKS PWM Clock Select These bits, together with bits PWCKB and PWCKA in PCSR, select the internal clock input to TCNT of the PWM.
Page 258: Pwm Data Registers 7 To 0 (Pwdr7 To Pwdr0)
Table 8.2 Internal Clock Selection PWSL PCSR PWCKE PWCKS PWCKB PWCKA Description — — — Clock input is disabled (Initial value) φ (system clock) is selected — — φ/2 is selected φ/4 is selected φ/8 is selected φ/16 is selected Resolution, PWM Conversion Period, and Carrier Frequency when φ...
Page 259: Pwm Data Polarity Register (Pwdpr)
8.3.3 PWM Data Polarity Register (PWDPR) PWDPR selects the PWM output phase. Bit Name Initial Value Description Output Select 7 to 0 These bits select the PWM output phase. Bits OS7 to OS0 correspond to outputs PW7 to PW0. 0: PWM direct output (PWDR value corresponds to high width of output) 1: PWM inverted output (PWDR value corresponds to low width of output)
Page 260: Peripheral Clock Select Register (Pcsr)
8.3.5 Peripheral Clock Select Register (PCSR) PCSR selects the PWM input clock. Bit Name Initial Value Description PWCKXC See section 9.3.4, Peripheral Clock Select Register PWCKXB (PCSR). PWCKXA 4 to — All 0 Reserved The initial value should not be changed. PWCKB PWM Clock Select B, A PWCKA...
Page 261: Operation
Operation The upper four bits of PWDR specify the duty cycle of the basic pulse as 0/16 to 15/16 with a resolution of 1/16. Table 8.4 shows the duty cycles of the basic pulse. Table 8.4 Duty Cycle of Basic Pulse Upper 4 Bits Basic Pulse Waveform (Internal) 0 1 2 3 4 5 6 7 8 9 A B C D E F 0...
Page 262: Figure 8.2 Example Of Additional Pulse Timing (When Upper 4 Bits In Pwdr = 1000)
The lower four bits in PWDR specify the position of pulses added to the 16 basic pulses. An additional pulse adds a high period (when OS = 0) with a width equal to the resolution before the rising edge of a basic pulse. When the upper four bits in PWDR are 0000, there is no rising edge of the basic pulse, but the timing for adding pulses is the same.
Page 263: Section 9 14-Bit Pwm Timer (Pwmx)
Section 9 14-Bit PWM Timer (PWMX) This LSI has an on-chip 14-bit pulse-width modulator (PWM) timer with two output channels. It can be connected to an external low-pass filter to operate as a 14-bit D/A converter. Features • Division of pulse into multiple base cycles to reduce ripple •...
Page 264: Input/Output Pins
Input/Output Pins Table 9.1 lists the PWMX (D/A) input and output pins. Table 9.1 Pin Configuration Name Symbol Function PWMX output pin 0 PWX0 Output PWM output of PWMX channel A PWMX output pin 1 PWX1 Output PWM output of PWMX channel B Register Descriptions The PWMX (D/A) has the following registers.
Page 265: Pwmx (D/A) Counters H And L (Dacnth And Dacntl)
9.3.1 PWMX (D/A) Counters H and L (DACNTH and DACNTL) DACNT is a 14-bit readable/writable up-counter. The input clock is selected by the CKS bit in DACR. DACNT functions as the timebase for both PWMX (D/A) channels. When a channel operates with 14-bit accuracy, it uses all DACNT bits.
Page 266: Pwmx (D/A) Data Registers A And B (Dadra And Dadrb)
9.3.2 PWMX (D/A) Data Registers A and B (DADRA and DADRB) DADRA corresponds to PWMX (D/A) channel A, and DADRB to PWMX (D/A) channel B. DADR cannot be accessed in 8-bit units. DADR should always be accessed in 16-bit units. For details, see section 9.4, Bus Master Interface.
Page 267 • DADRB Bit Name Initial Value Description DA13 D/A Data 13 to 0 DA12 Set a digital value to be converted to an analog value. DA11 In each base cycle, the DACNT value is continually DA10 compared with the DADR value to determine the duty cycle of the output waveform, and to decide whether to output a fine-adjustment pulse equal in width to the resolution.
Page 268: Pwmx (D/A) Control Register (Dacr)
9.3.3 PWMX (D/A) Control Register (DACR) DACR enables the PWM outputs, and selects the output phase and operating speed. Bit Name Initial Value Description  R/(W) Reserved The initial value should not be changed. PWME PWMX Enable Starts or stops DACNT. 0: DACNT operates as a 14-bit up-counter 1: DACNT halts at H'0003 ...
Page 269: Peripheral Clock Select Register (Pcsr)
9.3.4 Peripheral Clock Select Register (PCSR) PCSR and the CKS bit in DACR select the operating speed. Bit Name Initial Value Description PWCKXC PWMX Clock Select PWCKXB Select a clock cycle with the CKS bit in DACR of the PWCKXA PWMX being 1.
Page 270: Table 9.3 Access Method For Reading/Writing 16-Bit Registers
(2) Read When the upper byte is read from, the upper-byte value is transferred to the CPU and the lower- byte value is transferred to TEMP. Next, when the lower byte is read from, the lower-byte value in TEMP is transferred to the CPU. These registers should always be accessed in 16-bit units at a time with a MOV instruction, and the upper byte should always be accessed before the lower byte.
Page 271: Operation
Operation A PWM waveform like the one shown in figure 9.2 is output from the PWX pin. Data in DADR corresponds to the total width (T ) of the low (0) pulses output in one conversion cycle (256 pulses when CFS = 0, 64 pulses when CFS = 1). When OS = 0, this waveform is directly output. When OS = 1, the output waveform is inverted, and data in DADR value corresponds to the total width ) of the high (1) output pulses.
Page 272: Table 9.4 Settings And Operation (Examples When Φ = 20 Mhz)
Settings and Operation (Examples when φ φ φ φ = 20 MHz) Table 9.4 Conver-sion Fixed DADR Bits Resolution* Base Cycle Conversion Conversion Bit Data (µ µ µ µ s) Cycle TL/TH Cycle* Accuracy (µ µ µ µ s) (µ µ µ µ s) (µ...
Page 273: Figure 9.3 Output Waveform (Os = 0, Dadr Corresponds To T L )
1 conversion cycle f255 f256 L255 L256 = ··· = t = T 64 f255 f256 + ··· + t L255 L256 a. CFS = 0 [base cycle = resolution (T) 1 conversion cycle = ··· = t = T 256 + ···...
Page 274: Figure 9.4 Output Waveform (Os = 1, Dadr Corresponds To T H )
1 conversion cycle f255 f256 H255 H256 = ··· = t = T 64 f255 f256 + ··· + t H255 H256 a. CFS = 0 [base cycle = resolution (T) 1 conversion cycle = ··· = t = T 256 + ···...
Page 275: Figure 9.6 Output Waveform When Dadr = H'0207 (Os = 1)
1 conversion cycle Base cycle Base cycle Base cycle No. 0 No. 1 No. 63 Base pulse Additional pulse output location High width: 2/256 × (T) Additional pulse Base pulse 1/256 × (T) 2/256 × (T) Figure 9.6 Output Waveform when DADR = H'0207 (OS = 1) However, when CFS = 0 (base cycle = resolution (T) ×...
Page 276: Table 9.5 Locations Of Additional Pulses Added To Base Pulse (When Cfs = 1)
Table 9.5 Locations of Additional Pulses Added to Base Pulse (when CFS = 1) Rev. 1.00, 09/03, page 238 of 704...
Page 277: Section 10 16-Bit Free-Running Timer (Frt)
Section 10 16-Bit Free-Running Timer (FRT) This LSI has an on-chip 16-bit free-running timer (FRT) with two channels. The FRT operates on the basis of the 16-bit free-running counter (FRC), and outputs two independent waveforms, and measures the input pulse width and external clock periods. 10.1 Features •...
Page 278: Figure 10.1 Block Diagram Of 16-Bit Free-Running Timer
External clock Internal clock OCRAR/F (H/L) φ/2 φ/8 φ/32 FTCI Clock Clock selector OCRA (H/L) Compare-match A Comparator A FTOA Internal data bus Overflow FTOB FRC (H/L) Clear FTIA Compare-match B Comparator B Control logic FTIB FTIC OCRB (H/L) FTID Input capture ICRA (H/L) ICRB (H/L)
Page 279: Input/Output Pins
10.2 Input/Output Pins Table 10.1 lists the FRT input and output pins. Table 10.1 Pin Configuration Channel Name Symbol Function Counter clock input pin FTCI_0 Input FRC counter clock input Output compare A output pin FTOA_0 Output Output compare A output Output compare B output pin FTOB_0 Output...
Page 280: Free-Running Counter (Frc)
• Timer control register (TCR) • Timer output compare control register (TOCR) Note: OCRA_0 (OCRA_1) and OCRB_0 (OCRB_1) share the same address. Register selection is controlled by the OCRS bit in TOCR_0 (TOCR_1). ICRA_0 (ICRA_1), ICRB_0 (ICRB_1), and ICRC_0 (ICRC_1) share the same addresses with OCRAR_0 (OCRAR_1), OCRAF_0 (OCRAF_1), and OCRDM_0 (OCRDM_1).
Page 281: Output Compare Registers Ar And Af (Ocrar And Ocraf)
To ensure input capture, the input capture pulse width should be at least 1.5 system clocks (φ) for a single edge. When triggering is enabled on both edges, the input capture pulse width should be at least 2.5 system clocks (φ). ICRA to ICRD should always be accessed in 16-bit units;...
Page 282: Timer Interrupt Enable Register (Tier)
10.3.6 Timer Interrupt Enable Register (TIER) TIER enables and disables interrupt requests. Bit Name Initial Value Description ICIAE Input Capture Interrupt A Enable Selects whether to enable an interrupt request (ICIA) by the ICFA flag when the ICFA flag in TCSR is set to 1. 0: ICIA requested by ICFA is disabled 1: ICIA requested by ICFA is enabled ICIBE...
Page 283: Timer Control/Status Register (Tcsr)
Bit Name Initial Value Description OCIBE Output Compare Interrupt B Enable Selects whether to enable an interrupt request (OCIB) by the OCFB flag when the OCFB flag in TCSR is set to 0: OCIB requested by OCFB is disabled 1: OCIB requested by OCFB is enabled OVIE Timer Overflow Interrupt Enable Selects whether to enable an interrupt request (FOVI)
Page 284 Bit Name Initial Value Description ICFB R/(W)* Input Capture Flag B This status flag indicates that the FRC value has been transferred to ICRB by means of an input capture signal. When BUFEB = 1, ICFB indicates that the new FRC value has been transferred to ICRB by an input capture signal and the old ICRB value has been moved into ICRD.
Page 285 Bit Name Initial Value Description OCFA R/(W)* Output Compare Flag A This status flag indicates that the FRC value matches the OCRA value. [Setting condition] When FRC = OCRA [Clearing condition] Read OCFA when OCFA = 1, then write 0 to OCFA OCFB R/(W)* Output Compare Flag B This status flag indicates that the FRC value matches...
Page 286: Timer Control Register (Tcr)
10.3.8 Timer Control Register (TCR) TCR selects the rising or falling edge of the input capture signals, specifies the buffer operation, and selects the FRC clock source. Bit Name Initial Value Description IEDGA Input Edge Select A Selects the rising or falling edge of the input capture A signal (FTIA).
Page 287: Timer Output Compare Control Register (Tocr)
Bit Name Initial Value Description CKS1 Clock Select 1, 0 CKS0 Select clock source for FRC. 00: Count on internal clock φ/2 01: Count on internal clock φ/8 10: Count on internal clock φ/32 11: Count on rising edge of external clock input signal (FTCI) 10.3.9 Timer Output Compare Control Register (TOCR)
Page 288 Bit Name Initial Value Description OCRS Output Compare Register Select OCRA and OCRB share the same address. When this address is accessed, the OCRS bit selects which register is accessed. The operation of OCRA or OCRB is not affected. 0: OCRA is selected 1: OCRB is selected Output Enable A Enables or disables output of the output compare A...
Page 289: Operation
10.4 Operation 10.4.1 Pulse Output Figure 10.2 shows an example of 50%-duty pulses output with an arbitrary phase difference. When a compare match occurs while the CCLRA bit in TCSR is set to 1, the OLVLA and OLVLB bits are inverted by software. H'FFFF Counter clear OCRA...
Page 290: Operation Timing
10.5 Operation Timing 10.5.1 FRC Increment Timing Figure 10.3 shows the FRC increment timing with an internal clock source. Figure 10.4 shows the increment timing with an external clock source. The pulse width of the external clock signal must be at least 1.5 system clocks (φ). The counter will not increment correctly if the pulse width is shorter than 1.5 system clocks (φ).
Page 291: Output Compare Output Timing
10.5.2 Output Compare Output Timing A compare-match signal occurs at the last state when the FRC and OCR values match (at the timing when the FRC updates the counter value). When a compare-match signal occurs, the level selected by the OLVL bit in TOCR is output at the output compare output pin (FTOA or FTOB). Figure 10.5 shows the timing of this operation for compare-match A.
Page 292: Input Capture Input Timing
10.5.4 Input Capture Input Timing The rising or falling edge can be selected for the input capture input timing by the IEDGA to IEDGD bits in TCR. Figure 10.7 shows the usual input capture timing when the rising edge is selected.
Page 293: Buffered Input Capture Input Timing
10.5.5 Buffered Input Capture Input Timing ICRC and ICRD can operate as buffers for ICRA and ICRB, respectively. Figure 10.9 shows how input capture operates when ICRC is used as ICRA's buffer register (BUFEA = 1) and IEDGA and IEDGC are set to different values (IEDGA = 1 and IEDGC = 0, or IEDGA = 0 and IEDGC = 1), so that input capture is performed on both the rising and falling edges of FTIA.
Page 294: Timing Of Input Capture Flag Setting
CPU read cycle of ICRA or ICRC φ FTIA Input capture signal Figure 10.10 Buffered Input Capture Timing (BUFEA = 1) 10.5.6 Timing of Input Capture Flag Setting The input capture flag, ICFA, ICFB, ICFC, or ICFD, is set to 1 by the input capture signal. The FRC value is simultaneously transferred to the corresponding input capture register (ICRA, ICRB, ICRC, or ICRD).
Page 295: Timing Of Output Compare Flag Setting
10.5.7 Timing of Output Compare Flag Setting The output compare flag, OCFA or OCFB, is set to 1 by a compare-match signal generated when the FRC value matches the OCRA or OCRB value. This compare-match signal is generated at the last state in which the two values match, just before FRC increments to a new value.
Page 296: Automatic Addition Timing
10.5.9 Automatic Addition Timing When the OCRAMS bit in TOCR is set to 1, the contents of OCRAR and OCRAF are automatically added to OCRA alternately, and when an OCRA compare-match occurs, a write to OCRA is performed. Figure 10.14 shows the OCRA write timing. φ...
Page 297: Figure 10.16 Timing Of Input Capture Mask Signal Clearing
φ N + 1 ICRD + OCRDM × 2 Compare-match signal Input capture mask signal Figure 10.16 Timing of Input Capture Mask Signal Clearing Rev. 1.00, 09/03, page 259 of 704...
Page 298: Interrupt Sources
10.6 Interrupt Sources The FRT can request seven interrupts: ICIA to ICID, OCIA, OCIB, and FOVI. Each interrupt can be enabled or disabled by an interrupt enable bit in TIER. Independent signals are sent to the interrupt controller for each interrupt. Table 10.2 lists the sources and priorities of these interrupts. Table 10.2 FRT Interrupt Sources Channel Interrupt...
Page 299: Usage Notes
10.7 Usage Notes 10.7.1 Conflict between FRC Write and Clear If an internal counter clear signal is generated during the state after an FRC write cycle, the clear signal takes priority and the write is not performed. Figure 10.17 shows the timing for this type of conflict.
Page 300: Conflict Between Frc Write And Increment
10.7.2 Conflict between FRC Write and Increment If an FRC increment pulse is generated during the state after an FRC write cycle, the write takes priority and FRC is not incremented. Figure 10.18 shows the timing for this type of conflict. Write cycle of FRC φ...
Page 301: Conflict Between Ocr Write And Compare-Match
10.7.3 Conflict between OCR Write and Compare-Match If a compare-match occurs during the state after an OCRA or OCRB write cycle, the write takes priority and the compare-match signal is disabled. Figure 10.19 shows the timing for this type of conflict.
Page 302: Switching Of Internal Clock And Frc Operation
φ OCRAR (OCRAF) Address address Internal write signal Old data New data OCRAR (OCRAF) Compare-match signal Disabled Automatic addition is not performed because compare-match signals are disabled. Figure 10.20 Conflict between OCRAR/OCRAF Write and Compare-Match (When Automatic Addition Function is Used) 10.7.4 Switching of Internal Clock and FRC Operation When the internal clock is changed, the changeover may cause FRC to be incremented.
Page 303: Table 10.3 Switching Of Internal Clock And Frc Operation
Table 10.3 Switching of Internal Clock and FRC Operation Timing of Switchover by Means of CKS1 and CKS0 Bits FRC Operation Switching from Clock before switchover low to low Clock after switchover FRC clock N + 1 CKS bit rewrite Switching from Clock before switchover...
Page 304 Timing of Switchover by Means of CKS1 and CKS0 Bits FRC Operation Switching from Clock before switchover high to high Clock after switchover FRC clock N + 1 N + 2 CKS bit rewrite Note: * Generated on the assumption that the switchover is a falling edge; FRC is incremented. Rev.
Page 305: Section 11 8-Bit Timer (Tmr)
Section 11 8-Bit Timer (TMR) This LSI has an on-chip 2-system 8-bit timer module (TMR0 and TMR1) with two channels operating on the basis of an 8-bit counter. In addition to external event counting, the 8-bit timer module can be used as a multifunction timer in a variety of applications, such as generation of counter reset, interrupt requests, and pulse output with an arbitrary duty cycle using a compare- match signal with two registers.
Page 306: Figure 11.1 Block Diagram Of 8-Bit Timer (Tmr0 And Tmr1)
TMRX: Four types of interrupts: Compare-match A, compare-match B, overflow, and input capture Figures 11.1 and 11.2 show block diagrams of 8-bit timers. An input capture function is added to the TMRX. External clock Internal clock TMR1 TMR0 TMCI0 φ/2 φ/2 φ/64 φ/128...
Page 307: Figure 11.2 Block Diagram Of 8-Bit Timer (Tmry And Tmrx)
External clock Internal clock TMRY TMRX TMCIY φ φ TMCIX φ φ /256 φ φ /2048 Clock X Clock Y Select clock TCORAY TCORAX Compare match AX Compare match AY Comparator AY Comparator AX Overflow X TCNTY TCNTX Overflow Y Clear Y Clear X Compare match BX...
Page 308: Input/Output Pins
11.2 Input/Output Pins Table 11.1 summarizes the input and output pins of the TMR. Table 11.1 Pin Configuration Channel System Name Symbol Function TMR0 Timer output TMO0_0 Output Output controlled by compare- match Timer clock/reset TMI0_0/ Input External clock input input ExTMI0_0 (TMCI0)/external reset input...
Page 309: Register Descriptions
Channel System Name Symbol Function TMR0 Timer output TMO0_1 Output Output controlled by compare- match Timer clock/reset TMI0_1/ Input External clock input input ExTMI0_1 (TMCI0)/external reset input (TMRI0) for the counter TMR1 Timer output TMO1_1 Output Output controlled by compare- match Timer clock/reset TMI1_1/...
Page 310 TMRY_0: • Timer counter Y_0 (TCNTY_0) • Time constant register AY_0 (TCORAY_0) • Time constant register BY_0 (TCORBY_0) • Timer control register Y_0 (TCRY_0) • Timer control/status register Y_0 (TCSRY_0) • Timer input select register_0 (TISR_0) TMRX_0: • Timer counter X_0 (TCNTX_0) •...
Page 311: Timer Counter (Tcnt)
• Time constant register BY_1 (TCORBY_1) • Timer control register Y_1 (TCRY_1) • Timer control/status register Y_1 (TCSRY_1) • Timer input select register_1 (TISR_1) TMRX_1: • Timer counter X_1 (TCNTX_1) • Time constant register AX_1 (TCORAX_1) • Time constant register BX_1 (TCORBX_1) •...
Page 312: Timer Control Register (Tcr)
flag in TCSR is set to 1. Note however that comparison is disabled during the T2 state of a TCORB write cycle. The timer output from the TMO pin can be freely controlled by this compare- match B signal and the settings of the OS3 and OS2 bits in TCSR. TCORB is initialized to H'FF. 11.3.4 Timer Control Register (TCR) TCR selects the TCNT clock source and the condition by which TCNT is cleared, and...
Page 313: Table 11.2 Clock Input To Tcnt And Count Condition
Table 11.2 Clock Input to TCNT and Count Condition TECR System CKS2 Description CKS1 CKS0 ICKS1 ICKS0   TMR0 Disables clock input  Increments at falling edge of internal clock φ/8  Increments at falling edge of internal clock φ/2 ...
Page 314 TECR System CKS2 Description CKS1 CKS0 ICKS1 ICKS0   TMRY Increments at falling edge of internal clock φ/2048   Increments at overflow signal from TCNTX*   TMRX Disables clock input   Increments at falling edge of internal clock φ...
Page 315: Timer Control/Status Register (Tcsr)
11.3.5 Timer Control/Status Register (TCSR) TCSR indicates the status flags and controls compare-match output. • TCSR0 Bit Name Initial Value R/W Description CMFB R/(W)* Compare-Match Flag B [Setting condition] When the values of TCNT0 and TCORB0 match [Clearing condition] Read CMFB when CMFB = 1, then write 0 to CMFB CMFA R/(W)* Compare-Match Flag A...
Page 316 Bit Name Initial Value R/W Description Output Select 1, 0 Specify how the TMO0 pin output level is to be changed by compare-match A of TCORA0 and TCNT0. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) Notes: 1.
Page 317 Bit Name Initial Value R/W Description Output Select 3, 2 Specify how the TMO1 pin output level is to be changed by compare-match B of TCORB1 and TCNT1. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) Output Select 1, 0 Specify how the TMO1 pin output level is to be changed by compare-match A of TCORA1 and TCNT1.
Page 318 Bit Name Initial Value R/W Description R/(W)* Timer Overflow Flag [Setting condition] When TCNTY overflows from H'FF to H'00 [Clearing condition] Read OVF when OVF = 1, then write 0 to OVF ICIE Input Capture Interrupt Enable Enables or disables the ICF interrupt request (ICIX) when the ICF bit in TCSRX is set to 1.
Page 319 • TCSRX Bit Name Initial Value R/W Description CMFB R/(W)* Compare-Match Flag B [Setting condition] When the values of TCNTX and TCORBX match [Clearing condition] Read CMFB when CMFB = 1, then write 0 to CMFB CMFA R/(W)* Compare-Match Flag A [Setting condition] When the values of TCNTX and TCORAX match [Clearing condition]...
Page 320: Input Capture Register (Ticr)
Bit Name Initial Value R/W Description Output Select 1, 0 Specify how the TMOX pin output level is to be changed by compare-match A of TCORAX and TCNTX. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) Note: * Only 0 can be written to clear the flag.
Page 321: Timer Input Select Register (Tisr)
11.3.9 Timer Input Select Register (TISR) TISR selects a signal source of external clock/reset input for the counter. Bit Name Initial Value R/W Description 7 to 1  All 1 R/(W) Reserved The initial value should not be changed. Input Select Selects the internal synchronization signal (IVG signal) or timer clock/reset input pin (TMIY or ExTMIY) as the signal source of the external clock/reset input for the...
Page 322: Operation Timing
11.5 Operation Timing 11.5.1 TCNT Count Timing Figure 11.4 shows the TCNT count timing with an internal clock source. Figure 11.5 shows the TCNT count timing with an external clock source. The pulse width of the external clock signal must be at least 1.5 states for a single edge and at least 2.5 states for both edges. The counter will not increment correctly if the pulse width is less than these values.
Page 323: Timing Of Cmfa And Cmfb Setting At Compare-Match
11.5.2 Timing of CMFA and CMFB Setting at Compare-Match The CMFA and CMFB flags in TCSR are set to 1 by a compare-match signal generated when the TCNT and TCOR values match. The compare-match signal is generated at the last state in which the match is true, just when the timer counter is updated.
Page 324: Timing Of Counter Clear At Compare-Match
11.5.4 Timing of Counter Clear at Compare-Match TCNT is cleared when compare-match A or compare-match B occurs, depending on the setting of the CCLR1 and CCLR0 bits in TCR. Figure 11.8 shows the timing of clearing the counter by a compare-match.
Page 325: Tmr0 And Tmr1 Cascaded Connection
φ TCNT H'FF H'00 Overflow signal Figure 11.10 Timing of OVF Flag Setting 11.6 TMR0 and TMR1 Cascaded Connection If bits CKS2 to CKS0 in either TCR0 or TCR1 are set to B'100, the 2-system 8-bit timers are cascaded. With this configuration, 16-bit count mode in which the TMR0 and TMR1 are used as a single 16-bit timer or compare-match count mode in which the compare-match of the 8-bit timer (TMR0) is counted by the TMR1 can be selected.
Page 326: Compare-Match Count Mode
11.6.2 Compare-Match Count Mode When bits CKS2 to CKS0 in TCR1 are B'100, TCNT1 counts the occurrence of compare-match A for the TMR0. The TMR0 and TMR1 are controlled independently. Conditions such as setting of the CMF flag, generation of interrupts, output from the TMO pin, and counter clearing are in accordance with the settings for the TMR0 and TMR1.
Page 327: Compare-Match Count Mode
11.7.2 Compare-Match Count Mode When bits CKS2 to CKS0 in TCRX are B'100, TCNTX counts the occurrence of compare-match A for the TMRY. TMRY and TMRX are controlled independently. Conditions such as setting of the CMF flag, generation of interrupts, output from the TMO pin, and counter clearing are in accordance with the settings for the TMRY and TMRX.
Page 328: Figure 11.12 Timing Of Input Capture Signal (When Input Capture Signal Is Input During Ticrr And Ticrf Read)
TICRR, TICRF read cycle φ TMRIX Input capture signal Figure 11.12 Timing of Input Capture Signal (When Input Capture Signal is Input during TICRR and TICRF Read) Rev. 1.00, 09/03, page 290 of 704...
Page 329: Interrupt Sources
11.8 Interrupt Sources The TMR0, TMR1, and TMRY can generate three types of interrupts: CMIA, CMIB, and OVI. The TMRX can generate four types of interrupts: CMIA, CMIB, OVI, and ICIX. Table 11.3 shows the interrupt sources and priorities. Each interrupt source can be enabled or disabled independently by interrupt enable bits in TCR or TCSR.
Page 330: Usage Notes
11.9 Usage Notes 11.9.1 Conflict between TCNT Write and Clear If TCNT is cleared during the T state of a TCNT write cycle as shown in figure 11.13, the clear takes priority and TCNT is not written. TCNT write cycle by CPU φ...
Page 331: Conflict Between Tcnt Write And Increment
11.9.2 Conflict between TCNT Write and Increment If a TCNT input clock is generated during the T state of a TCNT write cycle as shown in figure 11.14, the write takes priority and the counter is not incremented. TCNT write cycle by CPU φ...
Page 332: Conflict Between Tcor Write And Compare-Match
11.9.3 Conflict between TCOR Write and Compare-Match If a compare-match occurs during the T state of a TCOR write cycle as shown in figure 11.15, the TCOR write takes priority and the compare-match signal is disabled. With the TMRX, a TICR input capture conflicts with a compare-match in the same way as with a write to TCORC.
Page 333: Switching Of Internal Clocks And Tcnt Operation
Table 11.4 Timer Output Priorities Output Setting Priority Toggle output High 1 output 0 output No change 11.9.5 Switching of Internal Clocks and TCNT Operation TCNT may be incremented erroneously when the internal clock is switched over. Table 11.5 shows the relationship between the timing at which the internal clock is switched (by writing to the CKS1 and CKS0 bits) and the TCNT operation.
Page 334: Table 11.5 Switching Of Internal Clocks And Tcnt Operation (Cont)
Table 11.5 Switching of Internal Clocks and TCNT Operation (cont) Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation Clock switching from low Clock before to high level∗ switchover Clock after switchover TCNT clock TCNT N + 1 N + 2 CKS bit rewrite Clock switching from high...
Page 335: Mode Setting With Cascaded Connection
11.9.6 Mode Setting with Cascaded Connection If 16-bit count mode and compare-match count mode are set simultaneously, the input clock pulses for TCNT0 and TCNT1 (or TCNTY and TCNTX) are not generated, and thus the counters will stop operating. Simultaneous setting of these two modes should therefore be avoided. Rev.
Page 336 Rev. 1.00, 09/03, page 298 of 704...
Page 337: Section 12 16-Bit Timer Pulse Unit (Tpu)
Section 12 16-Bit Timer Pulse Unit (TPU) This LSI has an on-chip 16-bit timer pulse unit (TPU) that comprises three 16-bit timer channels. The function list of the 16-bit timer pulse unit and its block diagram are shown in table 12.1 and figure 12.1, respectively.
Page 338: Figure 12.1 Block Diagram Of Tpu
Clock input φ/1 Internal clock: φ/4 φ/16 φ/64 φ/256 Internal data bus φ/1024 A/D conversion TCLKA External clock: start request signal TCLKB TCLKC TCLKD Input/output pins Interrupt request signals Channel 0: TGI0A Channel 0: TIOCA0 TGI0B TIOCB0 TGI0C TIOCC0 TGI0D TIOCD0 TCI0V Channel 1:...
Page 339: Table 12.1 Tpu Functions
Table 12.1 TPU Functions Item Channel 0 Channel 1 Channel 2 φ/1 φ/1 φ/1 Count clock φ/4 φ/4 φ/4 φ/16 φ/16 φ/16 φ/64 φ/64 φ/64 φ/256 φ/1024 TCLKA TCLKB TCLKA TCLKA TCLKC TCLKB TCLKB TCLKD TCLKC General registers TGRA_0 TGRA_1 TGRA_2 (TGR) TGRB_0...
Page 340 Item Channel 0 Channel 1 Channel 2 A/D conversion start TGRA_0 compare TGRA_1 compare TGRA_2 compare trigger match or input capture match or input capture match or input capture Interrupt sources 5 sources 4 sources 4 sources • • • Compare match or Compare match or Compare match or...
Page 341: Input/Output Pins
12.2 Input/Output Pins Table 12.2 Pin Configuration Channel Symbol Function TCLKA Input External clock A input pin (Channel 1 phase counting mode A phase input) TCLKB Input External clock B input pin (Channel 1 phase counting mode B phase input) TCLKC Input External clock C input pin...
Page 342: Register Descriptions
12.3 Register Descriptions The TPU has the following registers for each channel. Channel 0: • Timer control register_0 (TCR_0) • Timer mode register_0 (TMDR_0) • Timer I/O control register H_0 (TIORH_0) • Timer I/O control register L_0 (TIORL_0) • Timer interrupt enable register_0 (TIER_0) •...
Page 343: Timer Control Register (Tcr)
Common Registers: • Timer start register (TSTR) • Timer synchro register (TSYR) 12.3.1 Timer Control Register (TCR) TCR controls the TCNT operation for each channel. The TPU has a total of three TCR registers, one for each channel (channels 0 to 2). TCR settings should be made only when TCNT operation is stopped.
Page 344: Table 12.3 Cclr2 To Cclr0 (Channel 0)
Table 12.3 CCLR2 to CCLR0 (Channel 0) Bit 7 Bit 6 Bit 5 Channel CCLR2 CCLR1 CCLR0 Description TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation* TCNT clearing disabled...
Page 345: Table 12.5 Tpsc2 To Tpsc0 (Channel 0)
Table 12.5 TPSC2 to TPSC0 (Channel 0) Bit 2 Bit 1 Bit 0 Channel TPSC2 TPSC1 TPSC0 Description Internal clock: counts on φ/1 Internal clock: counts on φ/4 Internal clock: counts on φ/16 Internal clock: counts on φ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input External clock: counts on TCLKD pin input...
Page 346: Timer Mode Register (Tmdr)
Table 12.7 TPSC2 to TPSC0 (Channel 2) Bit 2 Bit 1 Bit 0 Channel TPSC2 TPSC1 TPSC0 Description Internal clock: counts on φ/1 Internal clock: counts on φ/4 Internal clock: counts on φ/16 Internal clock: counts on φ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input Internal clock: counts on φ/1024...
Page 347: Table 12.8 Md3 To Md0
Bit Name Initial Value Description Buffer Operation A Specifies whether TGRA is to operate in the normal way, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not generated. In channels 1 and 2, which have no TGRC, bit 4 is reserved.
Page 348: Timer I/O Control Register (Tior)
12.3.3 Timer I/O Control Register (TIOR) TIOR controls TGR. The TPU has a total of four TIOR registers, two for channel 0, and one each for channels 1 and 2. Care is required since TIOR is affected by the TMDR setting. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0).
Page 349: Table 12.9 Tiorh_0 (Channel 0)
Table 12.9 TIORH_0 (Channel 0) Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_0 IOB3 IOB2 IOB1 IOB0 Function TIOCB0 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 350: Table 12.10 Tiorh_0 (Channel 0)
Table 12.10 TIORH_0 (Channel 0) Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_0 IOA3 IOA2 IOA1 IOA0 Function TIOCA0 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 351: Table 12.11 Tiorl_0 (Channel 0)
Table 12.11 TIORL_0 (Channel 0) Description Bit 7 Bit 6 Bit 5 Bit 4 TGRD_0 IOD3 IOD2 IOD1 IOD0 Function TIOCD0 Pin Function Output Output disabled compare Initial output is 0 output register* 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 352: Table 12.12 Tiorl_0 (Channel 0)
Table 12.12 TIORL_0 (Channel 0) Description Bit 3 Bit 2 Bit 1 Bit 0 TGRC_0 IOC3 IOC2 IOC1 IOC0 Function TIOCC0 Pin Function Output Output disabled compare Initial output is 0 output register* 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 353: Table 12.13 Tior_1 (Channel 1)
Table 12.13 TIOR_1 (Channel 1) Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_1 IOB3 IOB2 IOB1 IOB0 Function TIOCB1 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 354: Table 12.14 Tior_1 (Channel 1)
Table 12.14 TIOR_1 (Channel 1) Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_1 IOA3 IOA2 IOA1 IOA0 Function TIOCA1 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 355: Table 12.15 Tior_2 (Channel 2)
Table 12.15 TIOR_2 (Channel 2) Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_2 IOB3 IOB2 IOB1 IOB0 Function TIOCB2 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 356: Table 12.16 Tior_2 (Channel 2)
Table 12.16 TIOR_2 (Channel 2) Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_2 IOA3 IOA2 IOA1 IOA0 Function TIOCA2 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 357: Timer Interrupt Enable Register (Tier)
12.3.4 Timer Interrupt Enable Register (TIER) TIER controls enabling or disabling of interrupt requests for each channel. The TPU has a total of three TIER registers, one for each channel. Bit Name Initial Value Description TTGE A/D Conversion Start Request Enable Enables or disables generation of A/D conversion start requests by TGRA input capture/compare match.
Page 358: Timer Status Register (Tsr)
Bit Name Initial Value Description TGIEB TGR Interrupt Enable B Enables or disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1. 0: Interrupt requests (TGIB) by TGFB disabled 1: Interrupt requests (TGIB) by TGFB enabled TGIEA TGR Interrupt Enable A Enables or disables interrupt requests (TGIA) by the...
Page 359 Bit Name Initial Value R/W Description TCFV R/(W)* Overflow Flag Status flag that indicates that TCNT overflow has occurred. [Setting condition] When the TCNT value overflows (change from H'FFFF to H'0000) [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 TGFD R/(W)* Input Capture/Output Compare Flag D Status flag that indicates the occurrence of TGRD input...
Page 360 Bit Name Initial Value R/W Description TGFB R/(W)* Input Capture/Output Compare Flag B Status flag that indicates the occurrence of TGRB input capture or compare match. [Setting conditions] • When TCNT = TGRB while TGRB is functioning as output compare register •...
Page 361: Timer Counter (Tcnt)
12.3.6 Timer Counter (TCNT) TCNT is a 16-bit readable/writable counter. The TPU has a total of three TCNT counters, one for each channel. TCNT is initialized to H'0000 by a reset, and in hardware standby mode. TCNT cannot be accessed in 8-bit units; it must always be accessed in 16-bit units. 12.3.7 Timer General Register (TGR) TGR is a 16-bit readable/writable register with a dual function as output compare and input...
Page 362: Timer Synchro Register (Tsyr)
12.3.9 Timer Synchro Register (TSYR) TSYR selects independent operation or synchronous operation for TCNT in channels 0 to 2. Synchronous operation is performed in the channel when the corresponding bit in TSYR is set to Bit Name Initial Value Description 7 to 3 ...
Page 363: Interface To Bus Master
12.4 Interface to Bus Master 12.4.1 16-Bit Registers TCNT and TGR are 16-bit registers. As the data bus to the bus master is 16 bits wide, these registers can be read from or written to in 16-bit units. These registers cannot be read from or written to in 8-bit units; 16-bit access must always be used. An example of 16-bit register access operation is shown in figure 12.2.
Page 364: Figure 12.4 8-Bit Register Access Operation [Bus Master ↔ Tmdr (Lower 8 Bits)]
Internal data bus Module master Bus interface data bus TMDR Figure 12.4 8-Bit Register Access Operation [Bus Master ↔ ↔ TMDR (Lower 8 Bits)] ↔ ↔ Internal data bus Module master Bus interface data bus TMDR Figure 12.5 8-Bit Register Access Operation [Bus Master ↔ ↔...
Page 365: Operation
12.5 Operation 12.5.1 Basic Functions Each channel has TCNT and TGR. TCNT performs up-counting, and is also capable of free- running operation, periodic counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Counter Operation: When one of bits CST0 to CST2 in TSTR is set to 1, TCNT for the corresponding channel starts counting.
Page 366: Figure 12.7 Free-Running Counter Operation
• Free-Running Count Operation and Periodic Count Operation Immediately after a reset, the TPU's TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1, the corresponding TCNT counter starts up- count operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1.
Page 367: Figure 12.8 Periodic Counter Operation
Counter cleared by TGR TCNT value compare match H'0000 Time CST bit Flag cleared by software or DMAC activation Figure 12.8 Periodic Counter Operation Waveform Output by Compare Match: The TPU can perform 0, 1, or toggle output from the corresponding output pin using compare match.
Page 368: Figure 12.10 Example Of 0 Output/1 Output Operation
• Examples of Waveform Output Operation Figure 12.10 shows an example of 0 output/1 output. In this example TCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B. When the set level matches the pin level, the pin level does not change.
Page 369: Figure 12.12 Example Of Setting Procedure For Input Capture Operation
• Example of Setting Procedure for Input Capture Operation Figure 12.12 shows an example of the setting procedure for input capture operation. Designate TGR as an input capture register by Input selection means of TIOR, and select rising edge, falling edge, or both edges as the input capture source and input signal edge.
Page 370: Synchronous Operation
12.5.2 Synchronous Operation In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base.
Page 371: Figure 12.15 Example Of Synchronous Operation
Example of Synchronous Operation: Figure 12.15 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source.
Page 372: Buffer Operation
12.5.3 Buffer Operation Buffer operation, provided for channel 0, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Table 12.17 shows the register combinations used in buffer operation.
Page 373: Figure 12.18 Example Of Buffer Operation Setting Procedure
Buffer operation Designate TGR as an input capture register or output compare register by means of TIOR. Designate TGR for buffer operation with bits BFA and BFB in TMDR. Select TGR function Set the CST bit in TSTR to 1 to start the count operation.
Page 374: Figure 12.20 Example Of Buffer Operation (2)
• When TGR is Input Capture Register Figure 12.20 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge.
Page 375: Cascaded Operation
12.5.4 Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 counter clock at overflow/underflow of TCNT_2 as set in bits TPSC2 to TPSC0 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase counting mode.
Page 376: Pwm Modes
TCNT_1 clock TCNT_1 H'03A1 H'03A2 TCNT_2 clock TCNT_2 H'FFFF H'0000 H'0001 TIOCA1, TIOCA2 TGRA_1 H'03A2 TGRA_2 H'0000 Figure 12.22 Example of Cascaded Operation (1) Figure 12.23 illustrates the operation when counting upon TCNT_2 overflow/underflow has been set for TCNT_1, and phase counting mode has been designated for channel 2. TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow.
Page 377: Table 12.19 Pwm Output Registers And Output Pins
PWM Mode 1: PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD. The value specified by bits IOA3 to IOA0 and IOC3 to IOC0 in TIOR is output from the TIOCA and TIOCC pins at compare matches A and C, and the value specified by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR is output at compare matches B and D.
Page 378: Figure 12.24 Example Of Pwm Mode Setting Procedure
• Example of PWM Mode Setting Procedure Figure 12.24 shows an example of the PWM mode setting procedure. Select the counter clock with bits TPSC2 to PWM mode TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR.
Page 379: Figure 12.26 Example Of Pwm Mode Operation (2)
Figure 12.26 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), to output a 5-phase PWM waveform.
Page 380: Figure 12.27 Example Of Pwm Mode Operation (3)
Figure 12.27 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode. TCNT value TGRB rewritten TGRA TGRB TGRB rewritten TGRB rewritten H'0000 Time 0% duty TIOCA Output does not change when periodic register and duty register compare matches occur simultaneously TCNT value TGRB rewritten...
Page 381: Phase Counting Mode
12.5.6 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1 and 2. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the settings of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR.
Page 382: Figure 12.29 Example Of Phase Counting Mode 1 Operation
Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. • Phase Counting Mode 1 Figure 12.29 shows an example of phase counting mode 1 operation, and table 12.21 summarizes the TCNT up/down-count conditions.
Page 383: Figure 12.30 Example Of Phase Counting Mode 2 Operation
• Phase Counting Mode 2 Figure 12.30 shows an example of phase counting mode 2 operation, and table 12.22 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count Down-count Time Figure 12.30 Example of Phase Counting Mode 2 Operation Table 12.22 Up/Down-Count Conditions in Phase Counting Mode 2...
Page 384: Figure 12.31 Example Of Phase Counting Mode 3 Operation
• Phase Counting Mode 3 Figure 12.31 shows an example of phase counting mode 3 operation, and table 12.23 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Down-count Up-count Time Figure 12.31 Example of Phase Counting Mode 3 Operation Table 12.23 Up/Down-Count Conditions in Phase Counting Mode 3...
Page 385: Figure 12.32 Example Of Phase Counting Mode 4 Operation
• Phase Counting Mode 4 Figure 12.32 shows an example of phase counting mode 4 operation, and table 12.24 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Down-count Up-count Time Figure 12.32 Example of Phase Counting Mode 4 Operation Table 12.24 Up/Down-Count Conditions in Phase Counting Mode 4...
Page 386: Interrupt Sources
12.6 Interrupt Sources 12.6.1 Interrupt Source and Priority There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disable bit, allowing generation of interrupt request signals to be enabled or disabled individually. When an interrupt source is generated, the corresponding status flag in TSR is set to 1.
Page 387: A/D Converter Activation
Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0.
Page 388: Operation Timing
12.7 Operation Timing 12.7.1 Input/Output Timing TCNT Count Timing: Figure 12.33 shows TCNT count timing in internal clock operation, and figure 12.34 shows TCNT count timing in external clock operation. φ Falling edge Rising edge Internal clock TCNT input clock TCNT Figure 12.33 Count Timing in Internal Clock Operation φ...
Page 389: Figure 12.35 Output Compare Output Timing
Output Compare Output Timing: A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output (TIOC) pin. After a match between TCNT and TGR, the compare match signal is not generated until the TCNT input clock is generated.
Page 390: Figure 12.37 Counter Clear Timing (Compare Match)
Timing for Counter Clearing by Compare Match/Input Capture: Figure 12.37 shows the timing when counter clearing by compare match occurrence is specified, and figure 12.38 shows the timing when counter clearing by input capture occurrence is specified. φ Compare match signal Counter clear signal H'0000...
Page 391: Figure 12.39 Buffer Operation Timing (Compare Match)
Buffer Operation Timing: Figures 12.39 and 12.40 show the timing in buffer operation. φ TCNT Compare match signal TGRA, TGRB TGRC, TGRD Figure 12.39 Buffer Operation Timing (Compare Match) φ Input capture signal TCNT TGRA, TGRB TGRC, TGRD Figure 12.40 Buffer Operation Timing (Input Capture) Rev.
Page 392: Interrupt Signal Timing
12.7.2 Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match: Figure 12.41 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and TGI interrupt request signal timing. φ TCNT input clock TCNT Compare match signal...
Page 393: Figure 12.42 Tgi Interrupt Timing (Input Capture)
TGF Flag Setting Timing in Case of Input Capture: Figure 12.42 shows the timing for setting of the TGF flag in TSR by input capture occurrence, and TGI interrupt request signal timing. φ Input capture signal TCNT TGF flag TGI interrupt Figure 12.42 TGI Interrupt Timing (Input Capture) TCFV Flag/TCFU Flag Setting Timing: Figure 12.43 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and...
Page 394: Figure 12.44 Tciu Interrupt Setting Timing
φ TCNT input clock TCNT H'0000 H'FFFF (underflow) Underflow signal TCFU flag TCIU interrupt Figure 12.44 TCIU Interrupt Setting Timing Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. Figure 12.45 shows the timing for status flag clearing by the CPU.
Page 395: Usage Notes
12.8 Usage Notes Input Clock Restrictions: The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a narrower pulse width.
Page 396: Figure 12.47 Contention Between Tcnt Write And Clear Operations
Contention between TCNT Write and Clear Operations: If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes priority and the TCNT write is not performed. Figure 12.47 shows the timing in this case. TCNT write cycle φ...
Page 397: Figure 12.49 Contention Between Tgr Write And Compare Match
Contention between TGR Write and Compare Match: If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes priority and the compare match signal is disabled. A compare match does not occur even if the same value as before is written to.
Page 398: Figure 12.51 Contention Between Tgr Read And Input Capture
Contention between TGR Read and Input Capture: If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data after input capture transfer. Figure 12.51 shows the timing in this case. TGR read cycle φ...
Page 399: Figure 12.53 Contention Between Buffer Register Write And Input Capture
Contention between Buffer Register Write and Input Capture: If the input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes priority and the write to the buffer register is not performed. Figure 12.53 shows the timing in this case.
Page 400: Figure 12.54 Contention Between Overflow And Counter Clearing
φ TCNT input clock TCNT H'FFFF H'0000 Counter clear signal Disabled TCFV Figure 12.54 Contention between Overflow and Counter Clearing Contention between TCNT Write and Overflow/Underflow: If there is an up-count or down-count in the T2 state of a TCNT write cycle and overflow/underflow occurs, the TCNT write takes priority and the TCFV/TCFU flag in TSR is not set.
Page 401 Multiplexing of I/O Pins: In this LSI, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input pin with the TIOCB2 I/O pin.
Page 402 Rev. 1.00, 09/03, page 364 of 704...
Page 403: Section 13 Timer Connection
Section 13 Timer Connection This LSI incorporates the timer connection with two channels. The timer connection allows interconnection by using the combination of input pins and I/O for a 16-bit free-running timer (FRT) and 8-bit timer (TMR1, TMRX, and TMRY). This capability can be used to implement complex functions such as PWM decoding and clamp waveform output.
Page 404: Figure 13.1 Schematic Diagram Of Timer Connection
VSYNCI_0 CBLANK CLAMPO HSYNCI_0 HSYNCO_0 Timer connection HSYNCO HSYNCO CSYNCI_0 Channel 0 output selection VFBACKI_0 VSYNCO_0 HFBACKI_0 VSYNCO VSYNCO output selection VSYNCI_1 HSYNCO_1 HSYNCI_1 Timer connection CSYNCI_1 Channel 1 VSYNCO_1 Figure 13.1 Schematic Diagram of Timer Connection Rev. 1.00, 09/03, page 366 of 704...
Page 405: Figure 13.2 Block Diagram Of Timer Connection
Figure 13.2 shows a block diagram of the timer connection. The configuration of the timer connection is the same in channels 0 and 1. However, the HFBACKI and VFBACKI inputs are not available in channel 1. Edge detection VSYNCI Phase READ / FTIA inversion...
Page 406: Input/Output Pins
13.2 Input/Output Pins Table 13.1 lists the timer connection input and output pins. Table 13.1 Pin Configuration Channel Name Abbreviation Function Vertical VSYNCI_0 Input Vertical synchronization signal synchronization input pin or FTIA_0 input pin signal input pin Horizontal HSYNCI_0 Input Horizontal synchronization signal synchronization input pin or TMI1_0 input pin...
Page 407: Register Descriptions
13.3 Register Descriptions The timer connection has the following registers in each channel. • Timer connection register I (TCONRI) • Timer connection register O (TCONRO) • Timer connection register S (TCONRS) • Edge sense register (SEDGR) • Timer extended control register (TECR) 13.3.1 Timer Connection Register I (TCONRI) TCONRI controls connection between timers, the signal source for synchronization signal input,...
Page 408 Bit Name Initial Value Description ICST Input Capture Start Bit The TMRX external reset input (TMRIX) is connected to the IHI signal. The TMRX has input capture registers (TICR, TICRR, and TICRF). TICRR and TICRF can measure the width of a short pulse by means of a single capture operation under the control of the ICST bit.
Page 409: Table 13.2 Synchronization Signal Connection Enable
Bit Name Initial Value Description HIINV Horizontal and Composite Synchronization Signal Inversion Selects inversion of the input phase of the horizontal synchronization signal (HSYNCI) and composite synchronization signal (CSYNCI). 0: The HSYNCI and CSYNCI pin states are used directly as the HSYNCI and CSYNCI inputs 1: The HSYNCI and CSYNCI pin states are inverted before use as the HSYNCI and CSYNCI inputs VIINV...
Page 410: Timer Connection Register O (Tconro)
13.3.2 Timer Connection Register O (TCONRO) TCONRO controls output signal output, phase inversion, etc. Bit Name Initial Value Description Output Enable Control enabling/disabling of output of the horizontal synchronization signal (HSYNCO), vertical CLOE synchronization signal (VSYNCO), and clamp CBOE waveform (CLAMPO) and blanking waveform (CBLANK) in channel 0.
Page 411 Bit Name Initial Value Description HOINV Horizontal Synchronization Signal Output Inversion Selects the signal output from the HSYNCO with the settings of the HS2, HS1, and HS0 bits in TECR. See table 13.3. VOINV Vertical Synchronization Signal Output Inversion Selects the signal output from the VSYNCO with the setting of the VS0 bit in TECR.
Page 412: Table 13.3 Hsynco Output Selection
Table 13.3 HSYNCO Output Selection TECR TCONRO_1 TCONRO_0 HSYNCO Output Signal HOINV HOINV  The IHO signal in channel 0 is used directly as the HSYNCO output  The IHO signal in channel 0 is inverted before use as the HSYNCO output ...
Page 413: Timer Connection Register S (Tconrs)
13.3.3 Timer Connection Register S (TCONRS) TCONRS selects whether to access TMRX or TMRY registers, and the signal source and generation method for the synchronization signal output. Bit Name Initial Value Description  Reserved The initial value should not be changed. ISGENE Internal Synchronization Signal Select Selects internal synchronization signals (IHG, IVG,...
Page 414 Bit Name Initial Value Description CLMOD1 Clamp Waveform Mode Select 1, 0 CLMOD0 Select the signal source for the CLO signal (clamp waveform) in channel 0. These bits are reserved in channel 1. The initial value should not be changed. •...
Page 415: Edge Sense Register (Sedgr)
13.3.4 Edge Sense Register (SEDGR) SEDGR detects a rising edge on the timer connection input pins and the occurrence of 2fH modification, and determines the phase of the IVI and IHI signals. Bit Name Initial Value Description VEDG R/(W)* VSYNCI Edge Detects a rising edge on the VSYNCI pin.
Page 416 Bit Name Initial Value Description VFEDG R/(W)* VFBACKI Edge Detects a rising edge on the VFBACKI pin in channel 0. This bit is reserved in channel 1. This bit is always read as 0 and cannot be modified. 0: [Clearing condition] When 0 is written to VFEDG after reading VFEDG = 1: [Setting condition] When a rising edge is detected on the VFBACKI pin...
Page 417: Timer Extended Control Register (Tecr)
Notes: 1. Only 0 can be written, to clear the flag. 2. The initial value is undefined since it depends on the pin state. 13.3.5 Timer Extended Control Register (TECR) TECR selects the HSYNCO and VSYNCO output signals and the count clock source for the TMR0 and TMR1.
Page 418: Operation
13.4 Operation 13.4.1 PWM Decoding (PDC Signal Generation) The timer connection and TMRX can be used to decode a PWM signal in which 0 and 1 are represented by the pulse width. To do this, a signal in which a rising edge is generated at regular intervals must be selected as the IHI signal.
Page 419: Figure 13.4 Timing Chart For Pwm Decoding
Table 13.5 Examples of TCR Settings Abbreviation Contents Description CMIEB Interrupts due to a compare-match and overflow are disabled CMIEA OVIE 4, 3 CCLR1, CCLR0 TCNT is cleared by the rising edge of the external reset signal (IHI signal) Internal clock: Incremented on φ 2 to 0 CKS2 to CKS0 Table 13.6 Examples of TCORB (Pulse Width Threshold) Settings...
Page 420: Clamp Waveform Generation (Cl1/Cl2/Cl3 Signal Generation)
13.4.2 Clamp Waveform Generation (CL1/CL2/CL3 Signal Generation) The timer connection and TMRX can be used to generate signals with different duty cycles and rising/falling edges (clamp waveforms) in synchronization with the input signal (IHI signal). Three clamp waveforms can be generated: the CL1, CL2, and CL3 signals. In addition, the CL4 signal can be generated using the TMRY.
Page 421: Figure 13.5 Block Diagram For Clamp Waveform Generation
Internal clock TCORA IHI signal Comparator A TMRI TCNT Clock Clear Clamp waveform Contol logic generator TICR Capture Comparator C CL2 CL3 TCORC TMRX Figure 13.5 Block Diagram for Clamp Waveform Generation IHI signal CL1 signal CL2 signal TCNT TCORA Figure 13.6 Timing Chart for Clamp Waveform Generation (CL1 and CL2 Signals) Rev.
Page 422: Figure 13.7 Timing Chart For Clamp Waveform Generation (Cl3 Signal)
IHI signal CL3 signal TCNT TICR + TCORC TICR Figure 13.7 Timing Chart for Clamp Waveform Generation (CL3 Signal) Rev. 1.00, 09/03, page 384 of 704...
Page 423: Measurement Of 8-Bit Timer Divided Waveform Period
13.4.3 Measurement of 8-Bit Timer Divided Waveform Period The timer connection, TMR1, and FRT can be used to measure the period of an IHI signal divided waveform. Since the TMR1 can be cleared by a rising edge of the inverted IVI signal, the rise and fall of the IHI signal divided waveform can be synchronized with the IVI signal.
Page 424: Table 13.7 Examples Of Tcr And Tcsr Settings
Table 13.7 Examples of TCR and TCSR Settings Register Abbreviation Contents Description TCR of TMR1 CMIEB Interrupts due to compare-match and overflow are disabled CMIEA OVIE 4, 3 CCLR1, CCLR0 11 TCNT is cleared by the rising edge of the external reset signal (inverse of the IVI signal) 2 to 0...
Page 425: 2Fh Modification Of Ihi Signal
IVI signal IHI signal divided waveform ICRB(4) ICRB(3) ICRB(2) ICRB(1) ICRB Figure 13.9 Timing Chart for Measurement of IVI Signal and IHI Signal Divided Waveform Periods 13.4.4 2fH Modification of IHI Signal By using the timer connection and FRT, even if there is a part of the IHI signal with twice the frequency, this can be eliminated.
Page 426: Figure 13.10 Block Diagram For 2Fh Modification Of Ihi Signal
Internal clock Clock IHI signal ICRD Capture 2fH mask generator Comparator M OCRDM 2fH modification signal Figure 13.10 Block Diagram for 2fH Modification of IHI Signal Table 13.8 Examples of TCR, TCSR, TCOR, and OCRDM Settings Register Abbreviation Contents Description TCR of FRT IEDGD FRC value is transferred to ICRD on the...
Page 427: Ivi Signal Fall Modification And Ihi Synchronization
IHI signal (without 2fH modification) IHI signal (with 2fH modification) Mask interval ICRD + OCRDM × 2 ICRD + OCRDM ICRD Figure 13.11 2fH Modification Timing Chart 13.4.5 IVI Signal Fall Modification and IHI Synchronization By using the timer connection and TMR1, the fall of the IVI signal can be shifted backward by the specified number of IHI signal waveforms.
Page 428: Figure 13.12 Block Diagram For Ivi Signal Fall Modification And Ihi Signal Operation
Examples of TCR, TCSR, and TCORB settings of the TMR1 are shown in table 13.9, and the fall modification and IHI synchronization timing chart is shown in figure 13.13. IVI signal IHI signal Clock TCNT Clear Vertical synchronization signal modification Comparator B TCORB Modification signal...
Page 429: Internal Synchronization Signal Generation (Ihg/Ivg/Cl4 Signal Generation)
Table 13.9 Examples of TCR, TCSR, and TCORB Settings Register Abbreviation Contents Description TCR of TMR1 CMIEB Interrupts due to compare-match and overflow are disabled CMIEA OVIE 4, 3 CCLR1, TCNT is cleared by the rising edge of the CCLR0 external reset signal (inverse of the IVI signal) 2 to 0...
Page 430: Figure 13.14 Block Diagram For Ivg Signal Generation
The contents of OCRA of the FRT can be updated by the automatic addition of the contents of OCRAR or OCRAF, alternately, each time a compare-match occurs. A value corresponding to the 0 interval of the IVG signal is written to OCRAR, and a value corresponding to the 1 interval of the IVG signal is written to OCRAF.
Page 431: Figure 13.15 Block Diagram For Ihg Signal Generation
IVG signal Internal clock TCORA Clear Comparator A Control logic IHG signal TCNT Clear Clock Comparator B TCORB TMRY Figure 13.15 Block Diagram for IHG Signal Generation Rev. 1.00, 09/03, page 393 of 704...
Page 432: Table 13.10 Examples Of Ocrar, Ocraf, Tocr, Tcora, Tcorb, Tcr, And Tcsr Settings
Table 13.10 Examples of OCRAR, OCRAF, TOCR, TCORA, TCORB, TCR, and TCSR Settings Register Abbreviation Contents Description TCR of TMRY CMIEB Interrupts due to compare-match and overflow are disabled CMIEA OVIE 4, 3 CCLR1, TCNT is cleared by compare-match A CCLR0 2 to 0 CKS2 to...
Page 433: Figure 13.16 Ivg Signal/Ihg Signal/Cl4 Signal Timing Chart
IVG signal OCRA (4) = OCRA (3) + OCRAR OCRA (3) = OCRA (2) + OCRAF OCRA (2) = OCRA (1) + OCRAR OCRA (1) = OCRA (0) + OCRAF OCRA 6 system clocks 6 system clocks 6 system clocks signal signal TCORA...
Page 434: Hsynco Output
13.4.7 HSYNCO Output With the HSYNCO output, the meaning of the signal source to be selected and use or non-use of modification varies according to the IHI signal source and the waveform required by an external circuitry. The HSYNCO output modes are shown in table 13.11. Table 13.11 HSYNCO Output Modes Mode IHI Signal...
Page 435: Vsynco Output
13.4.8 VSYNCO Output With the VSYNCO output, the meaning of the signal source to be selected and use or non-use of modification varies according to the IVI signal source and the waveform required by an external circuitry. The VSYNCO output modes are shown in table 13.12. Table 13.12 VSYNCO Output Modes Mode IVI Signal...
Page 436: Cblank Output
Mode IVI Signal IVO Signal Meaning of IVO Signal Separate VSYNCI IVI signal (without fall VSYNCI input (vertical synchronization mode input modification or IHI signal) is output directly synchronization) IVI signal (without fall Meaningless if VSYNCI input (vertical modification, with IHI synchronization signal) is synchronized synchronization) with HSYNCI input (horizontal...
Page 437: Section 14 Duty Measurement Circuit
Section 14 Duty Measurement Circuit This LSI has an on-chip duty measurement circuit which consists of an edge detection circuit, 8-bit counter, and capture register. This circuit can measure the duty by detecting edges of an external event signal and capturing the high-level period and cycle. Figure 14.1 shows a block diagram of the duty measurement circuit.
Page 438: Figure 14.1 Block Diagram Of Duty Measurement Circuit
/2048 /32768 /65536 Clock Clock selection Overflow Clear TWCNT HSYNCI_0 Input capture HSYNCI_1 Internal TWICR CSYNCI_0 data bus Control logic CSYNCI_1 HFBACKI_0 Edge HFBACKI_1 detector TWCR1 VSYNCI_0 VSYNCI_1 TWCR2 Interrupt signal TWOVI TWENDI [Legend] TWCNT: Free-running counter TWICR: Input capture register TWCR1: Duty measurement control register 1 TWCR2:...
Page 439: Input/Output Pins
14.2 Input/Output Pins Table 14.1 lists the input pins for the duty measurement circuit. Table 14.1 Pin Configuration Name Symbol Function Horizontal synchronization HSYNCI_0 Input Horizontal synchronization signal 0 signal 0 input pin input pin Horizontal synchronization HSYNCI_1 Input Horizontal synchronization signal 1 signal 1 input pin input pin Composite synchronization...
Page 440: Register Descriptions
14.3 Register Descriptions The duty measurement circuit has the following registers. • Free-running counter (TWCNT) • Input capture register (TWICR) • Duty measurement control register 1 (TWCR1) • Duty measurement control register 2 (TWCR2) 14.3.1 Free-Running Counter (TWCNT) TWCNT is an 8-bit readable/writable up-counter. The free-running count operation is performed by setting the FRC bit in TWCR1 to 1.
Page 441: Duty Measurement Control Register 1 (Twcr1)
14.3.3 Duty Measurement Control Register 1 (TWCR1) TWCR1 controls the free-running counter (TWCNT) and selects the TWCNT input clock and an external event signal whose duty is to be measured. Bit Name Initial Value R/W Description R/W Free-Running Counter When 1 is written to this bit, TWCNT operates as a free-running counter regardless of the state of the START bit.
Page 442: Duty Measurement Control Register 2 (Twcr2)
14.3.4 Duty Measurement Control Register 2 (TWCR2) TWCR2 controls enabling or disabling interrupt request signals, status flag indication, and duty measurement operation. Bit Name Initial Value R/W Description ENDIE R/W Duty Measurement End Interrupt Enable When the ENDF flag in TWCR2 is set to 1, this bit enables or disables an interrupt request by the ENDF flag.
Page 443 Bit Name Initial Value R/W Description START R/W Start When the FRC bit in TWCR1 is 0 and 1 is written to this bit, duty measurement will start. If this bit is read during duty measurement, 1 is read from this bit. If duty measurement ends, this bit is automatically cleared to 0.
Page 444: Operation
14.4 Operation 14.4.1 Duty Measurement for External Event Signal Figure 14.2 shows an example of duty measurement for the external event signal. 1. Select the external event signal whose duty needs to be measured by the IS2 to IS0 bits in TWCR1.
Page 445: Operation Timing
14.5 Operation Timing 14.5.1 TWCNT Count Timing Figure 14.3 shows the TWCNT count timing. Internal clock TWCNT input clock TWCNT Figure 14.3 TWCNT Count Timing 14.5.2 TWCNT Clear Timing by Setting START Bit Setting the START bit in TWCR2 to 1 starts duty measurement and then clears TWCNT. Figure 14.4 shows the TWCNT clear timing.
Page 446: Count Start Timing For Duty Measurement
14.5.3 Count Start Timing for Duty Measurement If a rising edge of the external event input is detected after the START bit in TWCR2 has been set to 1, a count enable signal is set. At this time, if the TWCNT input clock exists, TWCNT starts incrementing.
Page 447: Clear Timing For Start Bit When Duty Measurement Ends
14.5.5 Clear Timing for START Bit when Duty Measurement Ends When duty measurement ends, the START bit in TWCR2 is cleared to 0. Figure 14.7 shows the clear timing for the START bit when duty measurement ends. External signal Duty measurement end signal START bit Figure 14.7 Clear Timing for START Bit when Duty Measurement Ends...
Page 448: Set Timing For Overflow Flag (Ovf)
14.5.7 Set Timing for Overflow Flag (OVF) The overflow flag (OVF) in TWCR2 is set to 1 by the overflow signal which is output when TCNT overflows from H′FF to H′00. Figure 14.9 shows the OVF set timing. TWCNT N'FF N'00 Overflow signal Figure 14.9 Set Timing for OVF Flag...
Page 449: Usage Notes
14.7 Usage Notes 14.7.1 Conflict between TWCNT Write and Increment If a TWCNT increment pulse is generated during the T state of a TWCNT write cycle as shown in figure 14.10, the write takes priority and TWCNT is not incremented. TWCNT write cycle by CPU Address TWCNT address...
Page 450: Switching Of Internal Clock And Twcnt Operation
14.7.3 Switching of Internal Clock and TWCNT Operation The changeover may cause TWCNT to be incremented depending on the timing at which the internal clock is switched (bits CKS2 to CKS0 are rewritten). Table 14.3 shows the relationship between the timing and TCNT operation. The TWCNT clock is generated on detection of the falling edge of the internal clock.
Page 451 Timing of Switchover by Means of CKS2 to CKS0 Bits TWCNT Operation Switching from Clock high to low* before switchover Clock after switchover TWCNT clock TWCNT Switchover of CKS bit Switching from Clock high to high before switchover Clock after switchover TWCNT clock TWCNT Switchover of CKS bit...
Page 452: Switching Of External Event Signal And Operation Of Edge Detection Circuit
14.7.4 Switching of External Event Signal and Operation of Edge Detection Circuit When the external event signal is changed, the edge detection circuit may regard it as a rising or falling edge. Table 14.4 shows the relationship between the timing at which the external event signal is switched (bits IS2 to IS0 are rewritten) and operation of the edge detection circuit.
Page 453 Timing of Switchover by Means of IS2 to IS0 Bits Operation of Edge Detection Circuit Switching from External event signal high to low before switchover External event signal after switchover Rising edge detection signal Falling edge detection signal Switchover of IS bit Switching from External event signal high to high...
Page 454 Rev. 1.00, 09/03, page 416 of 704...
Page 455: Section 15 Watchdog Timer (Wdt)
Section 15 Watchdog Timer (WDT) This LSI incorporates the watchdog timer (WDT). The WDT is an 8-bit timer that can generate an internal reset signal or an internal NMI interrupt signal if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. When this watchdog timer function is not needed, the WDT can be used as an interval timer.
Page 456: Register Descriptions
15.2 Register Descriptions The WDT has the following registers. To prevent accidental overwriting, TCNT and TCSR have to be written to in a method different from normal registers. For details, see section 15.5.1, Notes on Register Access. For details on the system control register, see section 3.2.2, System Control Register (SYSCR).
Page 457 Bit Name Initial Value R/W Description Timer Enable When this bit is set to 1, TCNT starts counting. When this bit is cleared, TCNT stops counting and is initialized to H′00.  Reserved The initial value should not be changed. RST/NMI 0 Reset or NMI Selects whether an internal reset or an NMI interrupt is...
Page 458: Operation
15.3 Operation 15.3.1 Watchdog Timer Mode To use the WDT as a watchdog timer, set the WT/IT bit and the TME bit in TCSR to 1. While the WDT is used as a watchdog timer, if TCNT overflows without being rewritten because of a system malfunction or another error, an internal reset or NMI interrupt request is generated.
Page 459: Interval Timer Mode
15.3.2 Interval Timer Mode When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each time TCNT overflows, as shown in figure 15.3. Therefore, an interrupt can be generated at intervals. When TCNT overflows in interval timer mode, the OVF bit in TCSR is set to 1 and at the same time an interval timer interrupt (WOVI) is requested.
Page 460: Internal Reset Signal Generation Timing
15.3.3 Internal Reset Signal Generation Timing When TCNT overflows in watchdog timer mode, the OVF bit in TCSR is set to 1. When the RST/NMI bit is set to 1 here, the internal reset signal is generated for the entire LSI. The timing is shown in figure 15.5.
Page 461: Usage Notes
15.5 Usage Notes 15.5.1 Notes on Register Access TCNT and TCSR differ from other registers in being more difficult to write to. The procedures for writing to and reading from these registers are given below. (1) Writing to TCNT and TCSR These registers must be written to by a word transfer instruction.
Page 462: Conflict Between Timer Counter (Tcnt) Write And Increment
15.5.2 Conflict between Timer Counter (TCNT) Write and Increment Even if a timer counter clock pulse is generated during the T state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 15.7 shows this operation. TCNT write cycle φ...
Page 463: Section 16 Serial Communication Interface (Sci)
Section 16 Serial Communication Interface (SCI) This LSI has five independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial communication. Asynchronous serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA).
Page 464: Figure 16.1 Block Diagram Of Sci
Figure 16.1 shows a block diagram of the SCI. Module data bus SCMR φ Baud rate φ/4 generator φ/16 Transmission/ φ/64 reception control Parity generation Clock Parity check External clock [Legend] RSR: Receive shift register SCR: Serial control register RDR: Receive data register SSR: Serial status register...
Page 465: Input/Output Pins
16.2 Input/Output Pins Table 16.1 shows the input/output pins for the SCI. Table 16.1 Pin Configuration Channel Symbol* Function SCK0 Channel 0 clock input/output RxD0 Input Channel 0 receive data input TxD0 Output Channel 0 transmit data output SCK1 Channel 1 clock input/output RxD1 Input Channel 1 receive data input...
Page 466: Register Descriptions
16.3 Register Descriptions The SCI has the following registers for each channel. • Receive shift register (RSR) • Receive data register (RDR) • Transmit data register (TDR) • Transmit shift register (TSR) • Serial mode register (SMR) • Serial control register (SCR) •...
Page 467: Transmit Shift Register (Tsr)
16.3.4 Transmit Shift Register (TSR) TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then sends the data to the TxD pin. TSR cannot be directly accessed by the CPU.
Page 468 Bit Name Initial Value Description STOP Stop Bit Length (enabled only in asynchronous mode) Selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits In reception, only the first stop bit is checked regardless of the STOP bit setting. If the second stop bit is 0, it is treated as the start bit of the next transmit frame.
Page 469: Serial Control Register (Scr)
16.3.6 Serial Control Register (SCR) SCR is a register that performs enabling or disabling of SCI transfer operations and interrupt requests, and selection of the transfer clock source. For details on interrupt requests, see section 16.7, Interrupt Sources. Bit Name Initial Value Description Transmit Interrupt Enable...
Page 470 Bit Name Initial Value Description CKE1 Clock Enable 1, 0 CKE0 These bits select the clock source and SCK pin function. Asynchronous mode 00: Internal clock (SCK pin functions as I/O port.) 01: Internal clock (Outputs a clock of the same frequency as the bit rate from the SCK pin.) 1x: External clock (Inputs a clock with a frequency 16 times the bit...
Page 471: Serial Status Register (Ssr)
16.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. TDRE, RDRF, ORER, PER, and FER can only be cleared. Bit Name Initial Value Description TDRE R/(W)* Transmit Data Register Empty Indicates whether TDR contains transmit data.
Page 472 Bit Name Initial Value R/W Description R/(W)* Framing Error [Setting condition] • When the stop bit is 0 [Clearing condition] • When 0 is written to FER after reading FER = In 2-stop-bit mode, only the first stop bit is checked.
Page 473: Serial Interface Mode Register (Scmr)
16.3.8 Serial Interface Mode Register (SCMR) SCMR is a register that selects the SCI functions. Bit Name Initial Value Description  7 to 4 All 1 Reserved These bits are always read as 1 and cannot be modified. SDIR Data Transfer Direction Selects the serial/parallel conversion format.
Page 474: Bit Rate Register (Brr)
16.3.9 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 16.2 shows the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and clocked synchronous mode.
Page 475: Table 16.3 Examples Of Brr Settings For Various Bit Rates (Asynchronous Mode) (1)
Table 16.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) Operating Frequency φ φ φ φ (MHz) 2.097152 2.4576 Bit Rate Error Error Error Error (bit/s) 0.03 –0.04 –0.26 0.03 0.16 0.21 0.00 0.16 0.16 0.21 0.00 0.16 0.16 0.21...
Page 476: Table 16.3 Examples Of Brr Settings For Various Bit Rates (Asynchronous Mode) (2)
Table 16.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) Operating Frequency φ φ φ φ (MHz) 6.144 7.3728 Bit Rate Error Error Error Error (bit/s) –0.44 0.08 –0.07 0.03 0.16 0.00 0.00 0.16 0.16 0.00 0.00 0.16 0.16 0.00...
Page 477: Table 16.3 Examples Of Brr Settings For Various Bit Rates (Asynchronous Mode) (3)
Table 16.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (3) Operating Frequency φ φ φ φ (MHz) 14.7456 17.2032 Bit Rate Error Error Error Error (bit/s) –0.17 0.70 0.03 0.48 0.16 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 0.00...
Page 478: Table 16.4 Maximum Bit Rate For Each Operating Frequency (Asynchronous Mode)
Table 16.4 Maximum Bit Rate for Each Operating Frequency (Asynchronous Mode) Maximum Maximum Bit Rate Bit Rate φ φ φ φ (MHz) φ φ φ φ (MHz) (bit/s) (bit/s) 62500 9.8304 307200 2.097152 65536 312500 2.4576 76800 375000 93750 12.288 384000 3.6864 115200...
Page 479: Table 16.6 Brr Settings For Various Bit Rates (Clocked Synchronous Mode)
Table 16.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency φ φ φ φ (MHz) Bit Rate (bit/s)             2.5k 100k 250k 500k 2.5M [Legend] Blank: Setting prohibited. ...
Page 480: Operation In Asynchronous Mode
16.4 Operation in Asynchronous Mode Figure 16.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by transmit/receive data, a parity bit, and finally stop bits (high level). In asynchronous serial communication, the transmission line is usually held in the mark state (high level).
Page 481: Data Transfer Format
16.4.1 Data Transfer Format Table 16.8 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. For details on the multiprocessor bit, see section 16.5, Multiprocessor Communication Function. Table 16.8 Serial Transfer Formats (Asynchronous Mode) SMR Settings Serial Transmit/Receive Format and Frame Length...
Page 482: Receive Data Sampling Timing And Reception Margin In Asynchronous Mode
16.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization.
Page 483: Clock
16.4.3 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI’s transfer clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate.
Page 484: Sci Initialization (Asynchronous Mode)
16.4.4 SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, first clear the TE and RE bits in SCR to 0, then initialize the SCI as shown in figure 16.5. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure.
Page 485: Serial Data Transmission (Asynchronous Mode)
16.4.5 Serial Data Transmission (Asynchronous Mode) Figure 16.6 shows an example of the operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is cleared to 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR.
Page 486: Figure 16.7 Sample Serial Transmission Flowchart
[1] SCI initialization: Initialization The TxD pin is automatically designated as the transmit data Start transmission output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is Read TDRE flag in SSR enabled.
Page 487: Serial Data Reception (Asynchronous Mode)
16.4.6 Serial Data Reception (Asynchronous Mode) Figure 16.8 shows an example of the operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line, and if a start bit is detected, performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit.
Page 488: Table 16.9 Ssr Status Flags And Receive Data Handling
FER, PER, and RDRF flags to 0 before resuming reception. Figure 16.9 shows a sample flowchart for serial data reception. Table 16.9 SSR Status Flags and Receive Data Handling SSR Status Flags RDRF* ORER Receive Data Receive Error Type Lost Overrun error Transferred to RDR Framing error...
Page 489: Figure 16.9 Sample Serial Reception Flowchart (1)
[1] SCI initialization: Initialization The RxD pin is automatically designated as the receive data input Start reception pin. [2] [3] Receive error processing and break detection: Read ORER, PER, and If a receive error occurs, read the FER flags in SSR ORER, PER, and FER flags in SSR to identify the error.
Page 490: Figure 16.9 Sample Serial Reception Flowchart (2)
Error processing ORER = 1 Overrun error processing FER = 1 Break? Framing error processing Clear RE bit in SCR to 0 PER = 1 Parity error processing Clear ORER, PER, and FER flags in SSR to 0 <End> Figure 16.9 Sample Serial Reception Flowchart (2) Rev.
Page 491: Multiprocessor Communication Function
16.5 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data.
Page 492: Figure 16.10 Example Of Communication Using Multiprocessor Format (Transmission Of Data H'aa To Receiving Station A)
Transmitting station Serial communication line Receiving Receiving Receiving Receiving station A station B station C station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial H'01 H'AA data (MPB = 1) (MPB = 0) ID transmission cycle = Data transmission cycle = receiving station Data transmission to...
Page 493: Multiprocessor Serial Data Transmission
16.5.1 Multiprocessor Serial Data Transmission Figure 16.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same as those in asynchronous mode.
Page 494: Multiprocessor Serial Data Reception
16.5.2 Multiprocessor Serial Data Reception Figure 16.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR.
Page 495: Figure 16.13 Sample Multiprocessor Serial Reception Flowchart (1)
[1] SCI initialization: Initialization The RxD pin is automatically designated as the receive data input pin. Start reception [2] ID reception cycle: Set the MPIE bit in SCR to 1. Set MPIE bit in SCR to 1 [3] SCI status check, ID reception and Read ORER and FER flags in SSR comparison: Read SSR and check that the RDRF...
Page 496: Figure 16.13 Sample Multiprocessor Serial Reception Flowchart (2)
Error processing ORER = 1 Overrun error processing FER = 1 Break? Framing error processing Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 <End> Figure 16.13 Sample Multiprocessor Serial Reception Flowchart (2) Rev.
Page 497: Operation In Clocked Synchronous Mode
16.6 Operation in Clocked Synchronous Mode Figure 16.14 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses. One character in transfer data consists of 8-bit data. In data transmission, the SCI outputs data from one falling edge of the synchronization clock to the next.
Page 498: Serial Data Transmission (Clocked Synchronous Mode)
[1] Set the clock selection in SCR. Be sure Start initialization to clear bits RIE, TIE, TEIE, MPIE, TE, and RE to 0. Clear TE and RE bits in SCR to 0 [2] Set the data transfer format in SMR and SCMR.
Page 499: Figure 16.16 Sample Sci Transmission Operation In Clocked Synchronous Mode
5. If the TDRE flag is cleared to 0, the next transmit data is transferred from TDR to TSR, and serial transmission of the next frame is started. 6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the SCI maintains the output state of the last bit.
Page 500: Figure 16.17 Sample Serial Transmission Flowchart
[1] SCI initialization: Initialization The TxD pin is automatically designated as the transmit data output Start transmission pin. [2] SCI status check and transmit data Read TDRE flag in SSR write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0.
Page 501: Serial Data Reception (Clocked Synchronous Mode)
16.6.4 Serial Data Reception (Clocked Synchronous Mode) Figure 16.18 shows an example of SCI operation for reception in clocked synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with a synchronization clock input or output, starts receiving data, and stores the receive data in RSR.
Page 502: Figure 16.19 Sample Serial Reception Flowchart
[1] SCI initialization: Initialization The RxD pin is automatically designated as the receive data input pin. Start reception [2] [3] Receive error processing: If a receive error occurs, read the Read ORER flag in SSR ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0.
Page 503: Simultaneous Serial Data Transmission And Reception (Clocked Synchronous Mode)
16.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) Figure 16.20 shows a sample flowchart for simultaneous serial transmit and receive operations. After initializing the SCI, the following procedure should be used for simultaneous serial data transmit and receive operations. To switch from transmit mode to simultaneous transmit and receive mode, after checking that the SCI has finished transmission and the TDRE and TEND flags in SSR are set to 1, clear the TE bit in SCR to 0.
Page 504: Figure 16.20 Sample Flowchart Of Simultaneous Serial Transmission And Reception
[1] SCI initialization: Initialization The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data Start transmission/reception input pin, enabling simultaneous transmit and receive operations. Read TDRE flag in SSR [2] SCI status check and transmit data write: Read SSR and check that the TDRE...
Page 505: Interrupt Sources
16.7 Interrupt Sources Table 16.10 shows the interrupt sources in normal serial communication interface mode. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated.
Page 506: Table 16.10 Sci Interrupt Sources
Table 16.10 SCI Interrupt Sources Channel Name Interrupt Source Interrupt Flag Priority ERI0 Receive error ORER, FER, PER High RXI0 Receive data full RDRF TXI0 Transmit data empty TDRE TEI0 Transmit end TEND ERI1 Receive error ORER, FER, PER RXI1 Receive data full RDRF TXI1...
Page 507: Usage Notes
16.8 Usage Notes 16.8.1 Module Stop Mode Setting SCI operation can be disabled or enabled using the module stop control register. The initial setting is for SCI operation to be halted. Register access is enabled by clearing module stop mode. For details, see section 22, Power-Down Modes.
Page 508: Sci Operations During Mode Transitions
16.8.6 SCI Operations during Mode Transitions Transmission: Before making the transition to module stop, software standby, or subsleep mode, stop all operations (TE = TIE = TEIE = 0). TSR, TDR, and SSR are reset. The states of the output pins during each mode depend on the port settings, and the pins output a high-level signal after mode cancellation.
Page 509: Figure 16.22 Pin States During Transmission In Asynchronous Mode (Internal Clock)
Transition to Software standby software standby Transmission start Transmission end mode cancelled mode TE bit Port output pin input/output Port High output Start Stop Port input/output High output input/output output pin SCI TxD output Port Port TxD output Figure 16.22 Pin States during Transmission in Asynchronous Mode (Internal Clock) Transition to Software standby Transmission start...
Page 510: Figure 16.24 Sample Flowchart For Mode Transition During Reception
Reception Read RDRF flag in SSR [1] Data being received will be invalid. RDRF = 1 Read receive data in RDR [2] Module stop mode is included. RE = 0 Make transition to software standby mode etc. Cancel software standby mode etc. Change operating mode? Initialization RE = 1...
Page 511: Switching From Sck Pins To Port Pins
16.8.7 Switching from SCK Pins to Port Pins When SCK pins are switched to port pins after transmission has completed, pins are enabled for port output after outputting a low pulse of half a cycle as shown in figure 16.25. Low pulse of half a cycle SCK/Port 1.
Page 512 Rev. 1.00, 09/03, page 474 of 704...
Page 513: Section 17 I C Bus Interface 3 (Iic3)
Section 17 I C Bus Interface 3 (IIC3) This LSI has a four-channel I C bus interface 3 (IIC3). The I C bus interface conforms to and provides a subset of the Philips I C bus (inter-IC bus) interface functions. The register configuration that controls the I C bus differs partly from the Philips configuration, however.
Page 514: Figure 17.1 Block Diagram Of I
Transfer clock generation circuit Transmission/ ICCRA reception control circuit Output ICCRB control ICMR Noise canceler ICDRT Output ICDRS control Address Noise canceler comparator ICDRR Bus state determination circuit Arbitration ICSR determination circuit ICIER Interrupt Interrupt request [Legend] generator ICCRA: C bus control register A ICCRB: C bus control register B ICMR :...
Page 515: Figure 17.2 External Circuit Connections Of I/O Pins
SCL in SDA in (Master) SCL in SCL in SDA in SDA in (Slave 1) (Slave 2) Figure 17.2 External Circuit Connections of I/O Pins Rev. 1.00, 09/03, page 477 of 704...
Page 516: Input/Output Pins
17.2 Input/Output Pins Table 17.1 shows the pin configuration of the I C bus interface 3. Table 17.1 Pin Configuration Name Symbol Function Serial clock SCL0 IIC3_0 serial clock input/output Serial data SDA0 IIC3_0 serial data input/output Serial clock SCL1 IIC3_1 serial clock input/output Serial data SDA1...
Page 517: C Bus Control Register A (Iccra)
17.3.1 C Bus Control Register A (ICCRA) ICCRA enables or disables the I C bus interface, controls transmission or reception, and selects master or slave mode, transmission or reception, and transfer clock frequency in master mode. Bit Bit Name Initial Value R/W Description C Bus Interface Enable 0: This module is halted.
Page 518: C Bus Control Register B (Iccrb)
Table 17.2 Transfer Rate Bit 3 Bit 2 Bit 1 Bit 0 Transfer Rate CKS3 CKS2 CKS1 CKS0 Clock φ φ φ φ = 8 MHz φ φ φ φ = 10 MHz φ φ φ φ = 20 MHz φ/28 286 kHz 357 kHz...
Page 519 Bit Bit Name Initial Value R/W Description Start/Stop Condition Prohibit Controls the issue of start/stop conditions in master mode. To issue a start condition, write 1 to BBSY and 0 to SCP. Also follow this procedure when retransmitting a start condition.
Page 520: C Bus Mode Register (Icmr)
17.3.3 C Bus Mode Register (ICMR) ICMR controls a wait in master mode and selects the transfer bit count. Bit Bit Name Initial Value R/W Description  Reserved The write value should always be 0. WAIT Wait Insertion Bit Selects whether to insert a wait after data transfer except for the acknowledge bit in master mode.
Page 521: C Bus Interrupt Enable Register (Icier)
Bit Bit Name Initial Value R/W Description Bit Counter 2 to 0 Specify the number of bits to be transferred next. The data is transferred with one acknowledge bit added. BC2 to BC0 settings should be made during an interval between transfer frames.
Page 522 Bit Bit Name Initial Value R/W Description Receive Interrupt Enable Enables or disables the receive data full interrupt request (RXI) when receive data is transferred from ICDRS to ICDRR and the RDRF bit in ICSR is set to 1. The RXI can be canceled by clearing the RDRF or RIE bit to 0.
Page 523: C Bus Status Register (Icsr)
17.3.5 C Bus Status Register (ICSR) ICSR confirms interrupt request flags and status. Bit Bit Name Initial Value R/W Description TDRE Transmit Data Empty [Setting condition] • When data is transferred from ICDRT to ICDRS and ICDRT becomes empty [Clearing conditions] •...
Page 524 Bit Bit Name Initial Value R/W Description STOP Stop Condition Detection Flag [Setting condition] • When a stop condition is detected after frame transfer [Clearing condition] • When 0 is written to STOP after reading STOP = 1 Arbitration Lost Flag Indicates that arbitration was lost in master mode.
Page 525: Slave Address Register (Sar)
17.3.6 Slave Address Register (SAR) SAR sets slave addresses. When the chip is in slave mode, if the upper 7 bits in SAR match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave device. Bit Name Initial Value R/W Description 7 to 1 SVA6 to All 0...
Page 526: Slave Address Register B (Sarb)
17.3.8 Slave Address Register B (SARB) SARB sets slave addresses. When the chip is in slave mode, if the upper 7 bits in SARB match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave device. Bit Name Initial Value R/W Description 7 to 1 SVA6 to All 0...
Page 527: C Bus Status Register A (Icsra)
17.3.10 I C Bus Status Register A (ICSRA) ICSRA confirms slave address recognition flags. Bit Name Initial Value R/W Description AASA R/W Slave Address Recognition Flag A In slave receive mode, this flag is set to 1 if the upper 7 bits in the first frame following a start condition match bits SVA6 to SVA0 in SARA.
Page 528: C Bus Shift Register (Icdrs)
17.3.13 I C Bus Shift Register (ICDRS) ICDRS is a register that is used to transfer/receive data. In transmission, data is transferred from ICDRT to ICDRS and the data is sent from the SDA pin. In reception, data is transferred from ICDRS to ICDRR after one byte of data is received.
Page 529: Operation
17.4 Operation 17.4.1 C Bus Format Figure 17.3 shows the I C bus formats. Figure 17.4 shows the I C bus timing. The first frame following a start condition always consists of 8 bits. (a) I C bus format DATA Transfer bit count (n = 1 to 8) Transfer frame count...
Page 530: Master Transmit Operation
[Legend] Start condition. The master device drives SDA from high to low while SCL is high. SLA: Slave address R/W: Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0. Acknowledge.
Page 531: Figure 17.5 Operation Timing In Master Transmit Mode (1)
(master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 (master output) Slave address (slave output) TDRE TEND Address + R/ ICDRT Data 1 Data 2 ICDRS Address + R/ Data 1 User [4] Write data to ICDRT (second byte).
Page 532: Master Receive Operation
17.4.3 Master Receive Operation In master receive mode, the master device outputs the receive clock, receives data from the slave device, and returns an acknowledge signal. The operation timings in master receive mode are shown in figures 17.7 and 17.8. The reception procedure and operations in master receive mode are shown below.
Page 533: Figure 17.7 Operation Timing In Master Receive Mode (1)
Master transmit mode Master receive mode (master output) (master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 (slave output) TDRE TEND RDRF ICDRS Data 1 ICDRR Data 1 User [3] Read ICDRR [2] Read ICDRR (dummy read) processing...
Page 534: Slave Transmit Operation
17.4.4 Slave Transmit Operation In slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. The operation timings in slave transmit mode are shown in figures 17.9 and 17.10. The transmission procedure and operations in slave transmit mode are described below.
Page 535: Figure 17.9 Operation Timing In Slave Transmit Mode (1)
Slave receive mode Slave transmit mode (master output) (master output) (slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 (slave output) TDRE TEND ICDRT Data 1 Data 2 Data 3 ICDRS Data 1 Data 2...
Page 536: Slave Receive Operation
Slave receive mode Slave transmit mode (master output) (master output) (slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (slave output) TDRE TEND ICDRT ICDRS Data n ICDRR User [5] Clear TDRE processing [4] Read ICDRR (dummy read) [3] Clear TEND...
Page 537: Figure 17.11 Operation Timing In Slave Receive Mode (1)
4. The last-byte data is read by reading ICDRR. (master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 (master output) (slave output) (slave output) RDRF ICDRS Data 1 Data 2 ICDRR Data 1 User...
Page 538: Noise Canceler
17.4.6 Noise Canceler The logic levels at the SCL and SDA pins are latched internally via the noise canceler. Figure 17.13 shows a block diagram of the noise canceler. The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches match.
Page 539: Figure 17.14 Sample Flowchart For Master Transmit Mode
Start Initialize Read BBSY in ICCRB Test the status of the SCL and SDA lines. BBSY = 0 ? Set master transmit mode. Set MST = 1 and TRS = 1 in ICCRA Start condition issuance. Write BBSY = 1 and SCP = 0 Set transmit data for the first byte (slave address + R/W).
Page 540: Figure 17.15 Sample Flowchart For Master Receive Mode
Master receive mode Clear TEND, set master receive mode, and then clear TDRE.* Clear TEND in ICSR Set acknowledge to the transmit device.* Set TRS = 0 (ICCRA) Dummy reading of ICDDR* Clear TDRE in ICSR Wait for 1 byte to be received. Set ACKBT = 0 (ICIER) Check if (last receive Dummy reading of ICDRR...
Page 541: Figure 17.16 Sample Flowchart For Slave Transmit Mode
[1] Clear the AAS flag. Slave transmit mode Clear AAS in ICSR [2] Set transmit data to ICDRT (except for the last byte). [3] Wait for ICDRT empty. Write transmit data in ICDRT [4] Set the last byte of the transmit data. Read TDRE in ICSR [5] Wait the transmission end of the last byte.
Page 542: Figure 17.17 Sample Flowchart For Slave Receive Mode
Slave receive mode [1] Clear the AAS flag. Clear AAS in ICSR [2] Set the acknowledge for the transmit device. Set ACKBT = 0 in ICIER [3] Dummy reading of ICDRR. Dummy reading of ICDRR [4] Wait the reception end of 1 byte. [5] Test the (last receive Read RDRF in ICSR [6] Read the received data.
Page 543: Interrupt Requests
17.5 Interrupt Requests There are six interrupt requests in this module; transmit data empty, transmit end, receive data full, NACK detection, STOP recognition, and arbitration lost. Table 17.3 shows the contents of each interrupt request. Table 17.3 Interrupt Requests Interrupt Request Abbreviation Interrupt Condition Transmit data empty...
Page 544: Bit Synchronous Circuit
17.6 Bit Synchronous Circuit In master mode, • When the SCL is driven low by the slave device • When the rising speed of the SCL is lower by the load of the SCL line (load capacitance or pull-up resistance) This module has a possibility that the high level period may be short in the two states described above.
Page 545: Section 18 A/D Converter
Section 18 A/D Converter This LSI includes a successive-approximation-type 10-bit A/D converter that allows up to sixteen analog input channels to be selected. Figure 18.1 shows a block diagram of the A/D converter. 18.1 Features • 10-bit resolution • Sixteen input channels •...
Page 546: Figure 18.1 Block Diagram Of A/D Converter
Module data bus Internal data bus Vref 10-bit A/D – Comparator Control circuit Sample-and- hold circuit AN10 AN11 AN12 ADI interrupt signal AN13 AN14 Conversion start AN15 trigger from 8-bit timer or TPU [Legend] ADCR: A/D control register ADDRD: A/D data register D ADDRE: A/D data register E ADCSR: A/D control/status register ADDRF: A/D data register F...
Page 547: Input/Output Pins
18.2 Input/Output Pins Table 18.1 shows the pin configuration of the A/D converter. The AV and AV pins are the power supply pins for the analog block in the A/D converter. The Vref pin is the reference voltage pin for the A/D conversion. The sixteen analog input pins are divided into two channel sets: channel set 0 (AN0 to AN7) and channel set 1 (AN8 to AN15).
Page 548: Register Descriptions
18.3 Register Descriptions The A/D converter has the following registers. • A/D data register A (ADDRA) • A/D data register B (ADDRB) • A/D data register C (ADDRC) • A/D data register D (ADDRD) • A/D data register E (ADDRE) •...
Page 549: A/D Control/Status Register (Adcsr)
18.3.2 A/D Control/Status Register (ADCSR) ADCSR controls A/D conversion operations. Bit Name Initial Value Description R/(W)* A/D End Flag A status flag that indicates the end of A/D conversion. [Setting conditions] • When A/D conversion ends in single mode • When A/D conversion ends on all specified channels in scan mode [Clearing condition]...
Page 550 Bit Name Initial Value Description Channel Select 3 to 0 Select analog input together with the SCANE and SCANS bits in ADCRS. Set the input channel when conversion is stopped (ADST = 0). When SCANE = 0 and SCANS = x 0000: AN0 1000: AN8 0001: AN1...
Page 551: A/D Control Register (Adcr)
18.3.3 A/D Control Register (ADCR) ADCR enables an A/D conversion start by an external trigger input. Bit Name Initial Value Description TRGS1 Timer Trigger Select 1 and 0 TRGS0 Select enabling or disabling of the start of A/D conversion by a trigger signal. 00: A/D conversion start by external trigger is disabled 01: A/D conversion start by conversion start trigger...
Page 552: Operation
18.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes: single mode and scan mode. When changing the operating mode or analog input channel, to prevent incorrect operation, first clear the ADST bit in ADCSR to 0 to halt A/D conversion.
Page 553: Input Sampling And A/D Conversion Time
4. The ADST bit is not cleared automatically, and steps 2 and 3 are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops and the A/D converter enters the wait state. Then if the ADST bit is set to 1, A/D conversion starts again for the first channel in the channel set.
Page 554: External Trigger Input Timing
Table 18.3 A/D Conversion Time (Single Mode) CKS1 = 0 CKS1 = 1 CKS0 = 0 CKS0 = 1 CKS0 = 0 CKS0 = 1 Item Symbol Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. — —...
Page 555: Interrupt Source
φ Internal trigger signal ADST A/D conversion Figure 18.3 External Trigger Input Timing 18.5 Interrupt Source The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. Setting the ADIE bit to 1 enables an ADI interrupt request while the ADF bit in ADCSR is set to 1 after A/D conversion is completed.
Page 556: A/D Conversion Accuracy Definitions
18.6 A/D Conversion Accuracy Definitions This LSI’s A/D conversion accuracy definitions are given below. • Resolution The number of A/D converter digital output codes • Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 18.4). •...
Page 557: Figure 18.4 A/D Conversion Accuracy Definitions
Digital output Ideal A/D conversion characteristic Quantization error 1022 1023 1024 1024 1024 1024 Analog input voltage Figure 18.4 A/D Conversion Accuracy Definitions Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic Analog Offset error input voltage Figure 18.5 A/D Conversion Accuracy Definitions Rev.
Page 558: Usage Notes
18.7 Usage Notes 18.7.1 Module Stop Mode Setting Operation of the A/D converter can be disabled or enabled using the module stop control register. The initial setting is for operation of the A/D converter to be halted. Register access is enabled by clearing module stop mode.
Page 559: Influences On Absolute Accuracy
18.7.3 Influences on Absolute Accuracy Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute accuracy. Be sure to make the connection to an electrically stable GND such as AVss. Care is also required to insure that filter circuits do not interfere with digital signals on the mounting board, so acting as antennas.
Page 560: Figure 18.7 Example Of Analog Input Protection Circuit
If a filter capacitor is connected, the input currents at the analog input pins (AN0 to AN15) are averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (R ), an error will arise in the analog input pin voltage.
Page 561: Section 19 Ram
Section 19 RAM This LSI has 16 kbytes of on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data. The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control register (SYSCR).
Page 562 Rev. 1.00, 09/03, page 524 of 704...
Page 563: Section 20 Flash Memory (0.18-Μm F-Ztat Version)
20.1 Features • Size Product Classification ROM Size ROM Address H8S/2437 HD64F2437 256 kbytes H'000000 to H'03FFFF • Two flash-memory MATs according to LSI initiation mode The on-chip flash memory has two memory spaces in the same address space (hereafter referred to as memory MATs).
Page 564: Figure 20.1 Block Diagram Of Flash Memory
• Programming/erasing protection Sets protection against flash memory programming/erasing via hardware, software, or error protection. • Programmer mode This mode uses the PROM programmer. The user MAT and user boot MAT can be programmed. Internal address bus Internal data bus (16 bits) FCCS FPCS FECS...
Page 565: Mode Transition
20.1.1 Mode Transition When each mode pin and the FWE pin are set in the reset state and the reset is canceled, this LSI enters each operating mode as shown in figure 20.2. • Flash memory can be read in user mode, but cannot be programmed or erased. •...
Page 566: Mode Comparison
20.1.2 Mode Comparison The comparison table of programming and erasing related items about boot mode, user program mode, user boot mode, and programmer mode is shown in table 20.1. Table 20.1 Comparison of Programming Modes User program Programmer Boot mode mode User boot mode mode...
Page 567: Flash Memory Mat Configuration
20.1.3 Flash Memory MAT Configuration This LSI’s flash memory consists of the 256-kbyte user MAT and 8-kbyte user boot MAT. The start address is allocated to the same address in the user MAT and user boot MAT. Therefore, when the program execution or data access is performed between two MATs, the MAT must be switched by using FMATS.
Page 568: Block Division
20.1.4 Block Division The user MAT is divided into 64 kbytes (three blocks), 32 kbytes (one block), and 4 kbytes (eight blocks) as shown in figure 20.4. The user MAT can be erased in this divided-block units and the erase-block number of EB0 to EB11 is specified when erasing. →...
Page 569: Programming/Erasing Interface
20.1.5 Programming/Erasing Interface Programming/erasing is executed by downloading the on-chip program to the on-chip RAM and specifying the program address/data and erase block by using the interface register/parameter. The procedure program should be created by the user in user program mode and user boot mode. An overview of the procedure is given as follows.
Page 570 (2) Download of On-Chip Program The on-chip program is automatically downloaded by setting the flash key code register (FKEY) and the SCO bit in the flash code control/status register (FCCS), which are programming/erasing interface registers. The flash memory MAT is replaced to the embedded program storage area during downloading. Since the flash memory MAT cannot be read when programming/erasing, the procedure program, which is working from download to completion of programming/erasing, must be executed in the space other than the flash memory (for example, on-chip RAM).
Page 571: Input/Output Pins
20.2 Input/Output Pins Table 20.2 shows the flash memory pin configuration. Table 20.2 Pin Configuration Pin Name Function Input Reset Input Flash memory programming/erasing enable pin Input Sets operating mode of this LSI Input Sets operating mode of this LSI Input Sets operating mode of this LSI TxD1...
Page 572: Programming/Erasing Interface Registers
Table 20.3 Registers/Parameters and Target Modes Program- Download Initialization ming Erasure Read     Programming/ FCCS Erasing     FPCS Interface     FECS Registers   FKEY FMATS      ...
Page 573 (1) Flash Code Control/Status Register (FCCS) FCCS is configured by bits which request the monitor of the FWE pin state and error occurrence during programming or erasing flash memory and the download of the on-chip program. Initial Bit Name Value Description Flash Program Enable Monitors the signal level input to the FWE pin.
Page 574 Initial Bit Name Value Description WEINTE Program/Erase Enable Modifies the space for the interrupt vector table, when interrupt vector data is not read successfully during programming/erasing flash memory or switching between a user MAT and a user boot MAT. When this bit is set to 1, interrupt vector data is read from address spaces H'FF6000 to H'FF607F (on-chip RAM space), instead of from address spaces H'000000 to H'00007F...
Page 575 Initial Bit Name Value Description (R)/W* [Clearing condition] • When download is completed 1: A request in which the on-chip programming/erasing program is downloaded to the on-chip RAM occurs. [Setting conditions] When all of the following conditions are satisfied and 1 is set to this bit •...
Page 576 (3) Flash Erase Code Select Register (FECS) FECS selects download of the on-chip erasing program. Initial Bit Name Value Description  7 to 1 All 0 Reserved The initial value should not be changed. EPVB Erase Pulse Verify Block Selects the erasing program. 0: On-chip erasing program is not selected.
Page 577 (5) Flash MAT Select Register (FMATS) FMATS specifies whether the user MAT or user boot MAT is selected. Initial Bit Name Value Description 0/1* MAT Select These bits are in the user-MAT selection state when the 0/1* value other than H'AA is written and in the user-boot- MAT selection state when H′AA is written.
Page 578 (6) Flash Transfer Destination Address Register (FTDAR) FTDAR specifies the on-chip RAM address which is download destination of an on-chip program. This register must be set before setting the SCO bit in FCCS to 1. Initial Bit Name Value Description TDER Transfer Destination Address Setting Error This bit is set to 1 when the address specified by bits...
Page 579: Programming/Erasing Interface Parameters
20.3.2 Programming/Erasing Interface Parameters The programming/erasing interface parameters specify the operating frequency, storage place for program data, programming destination address, and erase block and exchange the processing result for the downloaded on-chip program. These parameters use the general registers of the CPU (ER0 and ER1) or the on-chip RAM area.
Page 580: Table 20.4 Parameters And Target Modes
Table 20.4 Parameters and Target Modes Name of Abbrevia- Down- Initializa- Program- Initial Alloca- Parameter tion load tion ming Erasure Value tion    Undefined Download DPFR On-chip pass/fail result RAM*  Flash pass/fail FPFR Undefined R0L of result ...
Page 581 Initial Bit Name Value Description    7 to 3 Unused Return 0.  Source Select Error Detect Only one type of the on-chip program which can be downloaded can be specified. When more than two types of programs are selected, the program is not selected, or the program is selected without being mapped, an error occurs.
Page 582 Initial Bit Name Value Description 31 to 16    Unused These bits should be cleared to 0. 15 to 0 F15 to F0  Frequency Set Set the operating frequency of the CPU. With the PLL multiplication function, set the frequency multiplied. The setting value must be calculated as the following methods.
Page 583 Initial Bit Name Value Description    7 to 2 Unused Return 0.  Frequency Error Detect Returns the check result whether the specified operating frequency of the CPU is in the range of the supported operating frequency. 0: Setting of operating frequency is normal 1: Setting of operating frequency is abnormal ...
Page 584 The start address of the programming destination must be at the 128-byte boundary. If this boundary condition is not satisfied, an error occurs. The error occurrence is indicated by the WA bit (bit 1) in FPFR. Initial Bit Name Value Description ...
Page 585 (c) Flash Pass/Fail Parameter (FPFR: General Register R0L of CPU) FPFR indicates the return value of the program processing result. Initial Value Bit Name Description    Unused Returns 0.  Error Detect for Programming Mode Related Setting Returns the check result that a high level signal is input to the FWE pin and the error protection state is not entered.
Page 586 Initial Bit Name Value Description    Unused Returns 0.  Program Data Address Detect When the address in the flash memory area is specified as the start address of the storage destination of the program data, an error occurs. 0: Setting of program data address is normal 1: Setting of program data address is abnormal ...
Page 587 (4) Erasure Execution When flash memory is erased, the erase-block number in the user MAT must be transferred to the erasing program which is downloaded. This is set to FEBS (general register ER0). One block is specified from the block number 0 to 11. For details on the erasing processing procedure, see section 20.4.2, User Program Mode.
Page 588 (b) Flash Pass/Fail Parameter (FPFR: General Register R0L of CPU) FPFR indicates a return value of the erasing processing result. Initial Value Bit Name Description    Unused Returns 0.  Error Detect for Erasing Mode Related Setting Returns the check result that a high level signal is input to the FWE pin and the error protection state is not entered.
Page 589: On-Board Programming Mode
Initial Bit Name Value Description    2, 1 Unused Return 0.  Success/Fail Indicates whether the erasing processing is ended normally or not. 0: Erasure is ended normally (no error) 1: Erasure is ended abnormally (error occurs) 20.4 On-Board Programming Mode When the pin is set in on-board programming mode and the reset start is executed, the on-board programming state that can program/erase the on-chip flash memory is entered.
Page 590: Figure 20.6 System Configuration In Boot Mode
The system configuration diagram in boot mode is shown in figure 20.6. For details on the pin setting in boot mode, see table 20.5. The NMI and other interrupts are ignored in boot mode. However, the NMI and other interrupts should be disabled in the system. This LSI Control command, Flash...
Page 591: Table 20.6 System Clock Frequency For Automatic-Bit-Rate Adjustment
Table 20.6 System Clock Frequency for Automatic-Bit-Rate Adjustment Bit Rate of Host System Clock Frequency which can Automatically Adjust Bit Rate of this LSI 4,800 bps 5 to 20 MHz 9,600 bps 5 to 20 MHz 19,200 bps 5 to 20 MHz (2) State Transition Diagram The overview of the state transition diagram after boot mode is initiated is shown in figure 20.8.
Page 592: Figure 20.8 Overview Of State Transition Diagram In Boot Mode
(Bit rate adjustment) H'00, ..., H'00 reception H'00 transmission (adjustment completed) Boot mode initiation Bit rate adjustment (reset by boot mode) Inquiry command reception Processing of Wait for inquiry inquiry setting setting command command Inquiry command response All user MAT and user boot MAT erasure Read/check command reception...
Page 593: User Program Mode
20.4.2 User Program Mode The user MAT can be programmed/erased in user program mode. (The user boot MAT cannot be programmed/erased.) Programming/erasing is executed by downloading the program in the microcomputer. The overview of programming/erasing flow is shown in figure 20.9. High voltage is applied to the internal flash memory during programming/erasing processing.
Page 594: Figure 20.10 Ram Map When Programming/Erasing Is Executed
(1) On-chip RAM Address Map when Programming/Erasing is Executed Some of the procedure programs that should be created by the user, such as a download request, programming/erasing procedure, and determination of the result, must be executed in the on-chip RAM. The on-chip programs to be downloaded are all in the on-chip RAM. Note that area in the on-chip RAM must be controlled so that these programs do not overlap.
Page 595: Figure 20.11 Programming Procedure
(2) Programming Procedure in User Program Mode The procedures for download, initialization, and programming are shown in figure 20.11. Start programming procedure program Select on-chip program to be downloaded and Disable interrupts and bus specify download master operation destination by FTDAR other than CPU Set FKEY to H'A5 Set FKEY to H'5A...
Page 596 128-byte programming is performed in one program processing. When more than 128-byte programming is performed, programming destination address/program data parameter is updated in 128-byte units and programming is repeated. When less than 128-byte programming is performed, data size must be128 bytes by adding the invalid data.
Page 597 • In download processing, all interrupts are not accepted. However, interrupt requests other than the NMI are retained. Therefore, when the user procedure program is returned, the interrupts occur. • When the level-detection interrupt requests need to be retained, interrupts must be input until the download is ended.
Page 598 • Since the stack area is used in the initialization program, 128-byte stack area at the maximum must be saved in RAM. • Interrupts can be accepted during the execution of the initialization program. The program storage area and stack area in the on-chip RAM and register values must not be destroyed. 8.
Page 599 ; Set entry address to ER2 MOV.L #DLTOP+16,ER2 ; Call programming routine @ER2 • The general registers other than R0L are retained in the programming program. • R0L is a return value of FPFR. • Since the stack area is used in the programming program, a stack area of 128 bytes at the maximum must be saved in RAM.
Page 600: Figure 20.12 Erasing Procedure
(3) Erasing Procedure in User Program Mode The procedures for download, initialization, and erasing are shown in figure 20.12. Start erasing procedure program Select on-chip program to be downloaded and Disable interrupts and specify download bus master operation destination by FTDAR other than CPU Set FKEY to H'A5 Set FKEY to H'5A...
Page 601 A single divided block is erased in one erasing processing. For block divisions, see figure 20.4. To erase two or more blocks, update the erase block number and perform the erasing processing for each block. 1. Select the on-chip program to be downloaded Set the EPVB bit in FECS to 1.
Page 602: Figure 20.13 Repeating Procedure Of Erasing And Programming
(4) Erasing and Programming Procedure in User Program Mode By changing the on-chip RAM address of the download destination in FTDAR, the erasing program and programming program can be downloaded to separate on-chip RAM areas. Figure 20.13 shows a repeating procedure of erasing and programming. Start procedure program Specify a download destination of erasing...
Page 603: User Boot Mode
20.4.3 User Boot Mode This LSI has user boot mode which is initiated with different mode pin settings from those in boot mode or user program mode. User boot mode is a user-arbitrary boot mode, unlike boot mode that uses the on-chip SCI. Only the user MAT can be programmed/erased in user boot mode.
Page 604: Figure 20.14 Procedure For Programming User Mat In User Boot Mode
Start programming procedure program Select on-chip program to be downloaded and specify download destination by FTDAR Set FMATS to value other than H'AA to select user MAT switchover Set FKEY to H'A5 Set FKEY to H'5A Set SCO to 1 and execute download Set parameter to ER0 and ER1 (FMPAR and FMPDR)
Page 605: Figure 20.15 Procedure For Erasing User Mat In User Boot Mode
Except for MAT switching, the programming procedure is the same as that in user program mode. The area that can be executed in the steps of the user procedure program (on-chip RAM, user MAT, and external space) is shown in section 20.4.4, Storable Area for Procedure Program and Program Data.
Page 606: Storable Area For Procedure Program And Program Data
The difference between the erasing procedures in user program mode and user boot mode depends on whether the MAT is switched or not as shown in figure 20.15. MAT switching is enabled by writing a specific value to FMATS. However, note that while the MATs are being switched, the LSI is in an unstable state, e.g.
Page 607: Table 20.7 Executable Mat
Transitions to the reset state, and hardware standby mode are prohibited during programming/erasing. When the reset signal is accidentally input to the chip, a longer period in the reset state than usual (100 µs) is needed before the reset signal is released. 7.
Page 608: Table 20.8 (1) Usable Area For Programming In User Program Mode
Table 20.8 (1) Usable Area for Programming in User Program Mode Storable/Executable Area Selected MAT External Space Embedded On-chip User (Extended Program Item Mode) User MAT Storage MAT ×*   Storage area for program data Operation for selection of on-chip program to be downloaded Operation for writing H'A5 to FKEY...
Page 609 Storable/Executable Area Selected MAT External Space Embedded (Extended Program Item On-chip RAM User MAT Mode) User MAT Storage MAT × × Execution of programming × Determination of program result × Operation for program error × Operation for FKEY clear Note: * Transferring the data to the on-chip RAM enables this area to be used.
Page 610: Table 20.8 (2) Usable Area For Erasure In User Program Mode
Table 20.8 (2) Usable Area for Erasure in User Program Mode Storable/Executable Area Selected MAT External Space Embedded User (Extended Program Item On-chip RAM Mode) User MAT Storage MAT Operation for selection of on-chip program to be downloaded Operation for writing H'A5 to FKEY ×...
Page 611 Storable/Executable Area Selected MAT External Space Embedded User (Extended Program Item On-chip RAM Mode) User MAT Storage MAT × Operation for erasure error × Operation for FKEY clear Rev. 1.00, 09/03, page 573 of 704...
Page 612: Table 20.8 (3) Usable Area For Programming In User Boot Mode
Table 20.8 (3) Usable Area for Programming in User Boot Mode Storable/Executable Area Selected MAT External Embedded Space Program On-chip User Boot (Expanded User Boot Storage Item Mode) User MAT ×*    Storage area for program data Operation for selection of on-chip program to be downloaded...
Page 613 Storable/Executable Area Selected MAT External Embedded Space Program On-chip User Boot (Extended User Boot Storage Item Mode) User MAT × Operation for settings of program parameter × × Execution of programming × Determination of program result ×* Operation for program error ×...
Page 614: Table 20.8 (4) Usable Area For Erasure In User Boot Mode
Table 20.8 (4) Usable Area for Erasure in User Boot Mode Storable/Executable Area Selected MAT External Embedded Space Program On-chip User Boot (Extended User Boot Storage Item Mode) User MAT Operation for selection of on-chip program to be downloaded Operation for writing H'A5 to FKEY ×...
Page 615 Storable/Executable Area Selected MAT User Boot External User Boot Embedded On-chip Space User MAT Program Item (Extended Storage Mode) × × Execution of erasure × Determination of erasure result ×* Operation for erasure error × Operation for FKEY clear × ×...
Page 616: Protection
20.5 Protection There are three kinds of flash memory program/erase protection: hardware, software, and error protection. 20.5.1 Hardware Protection Programming and erasing of flash memory is forcibly disabled or suspended by hardware protection. In this state, the downloading of an on-chip program and initialization are possible. However, an activated program for programming or erasure cannot program or erase the user MAT, and the error in programming/erasing is reported in the parameter FPFR.
Page 617: Software Protection
20.5.2 Software Protection Software protection is set up in any of two ways: by disabling the downloading of on-chip programs for programming and erasing and by means of a key code. Table 20.10 Software Protection Function to be Protected Item Description Download Program/Erase •...
Page 618: Switching Between User Mat And User Boot Mat
Figure 20.16 shows state transitions to and from the error-protection state. Reset or hardware Program mode standby = 0 or Erase mode (Hardware protection) Read disabled, Read disabled, programming/erasing disabled, programming/erasing FLER = 0 enabled, FLER = 0 Program/erase interface register is in its initial state.
Page 619: Figure 20.17 Switching Between User Mat And User Boot Mat
< User MAT > < On-chip RAM > < User boot MAT > Procedure for switching to the user boot MAT Procedure for switching to the user MAT Procedure for switching to the user boot MAT (1) Mask interrupts (2) Write H'AA to FMATS. (3) Execute four NOP instructions before accessing the user boot MAT.
Page 620: Programmer Mode
PROM programmer can freely be used to program programs to the on-chip ROM. Program/erase is possible on the user MAT and user boot MAT. The PROM programmer must support Renesas Technology microcomputers with 256-kbyte flash memory as a device type*. Figure 20.18 shows a memory map in programmer mode.
Page 621: Serial Communication Interface Specification For Boot Mode
20.8 Serial Communication Interface Specification for Boot Mode Initiating boot mode enables the boot program to communicate with the host by using the internal SCI. The serial communication interface specification is shown below. (1) Status The boot program has three states. 1.
Page 622: Figure 20.19 Boot Program States
Reset Bit-rate-adjustment state Inquiry/response wait Inquiry Response Operations for Operations for Transition to inquiry and selection response programming/erasing Operations for erasing user MATs and user boot MATs Programming/erasing wait Programming Erasing Checking Operations for Operations for programming erasing Operations for checking Figure 20.19 Boot Program States Rev.
Page 623: Figure 20.20 Bit-Rate-Adjustment Sequence
(2) Bit-Rate-Adjustment State The bit rate is calculated by measuring the period of transfer of a low-level byte (H'00) from the host. The bit rate can be changed by the command for a new bit rate selection. After the bit rate has been adjusted, the boot program enters the inquiry/selection state.
Page 624: Figure 20.21 Communication Protocol Format
One-byte command Command or response or one-byte response n-byte command or Data n-byte response Size Checksum Command or response Error response Error code Error response Address Data (n bytes) 128-byte programming Command Checksum Memory read Data Size response Response Checksum Figure 20.21 Communication Protocol Format •...
Page 625: Table 20.11 Inquiry/Selection Commands
(4) Inquiry/Selection States The boot program returns information from the flash memory in response to the host’s inquiry commands and selects the device code, clock mode, and bit rate in response to the host’s selection command. Inquiry/selection commands are listed below. Table 20.11 Inquiry/Selection Commands Command Command Name Description...
Page 626 All of these commands, except for the boot program status inquiry command (H'4F), will be valid until the boot program receives the transition to programming/erasing state command (H'40). The host can select the needed commands out of the commands listed above and inquire them. The boot program status inquiry command (H'4F) is valid after the boot program has received the transition to programming/erasing state command (H'40).
Page 627 • Device code (four bytes): Device code (ASCII code) returned in response to the supported device inquiry • SUM (one byte): Checksum Response H'06 • Response, H'06, (one byte): Response to the device selection command ACK will be returned when the device code matches. Error response H'90 ERROR...
Page 628 • Response, H'06, (one byte): Response to the clock mode selection command ACK will be returned when the clock mode matches. Error Response H'91 ERROR • Error response, H'91, (one byte) : Error response to the clock mode selection command •...
Page 629 (f) Operating Clock Frequency Inquiry The boot program will return the number of operating clock frequencies, and the maximum and minimum values. Command H'23 • Command, H'23, (one byte): Inquiry regarding operating clock frequencies Response H'33 Size Number of operating clock frequencies Minimum value of Maximum value of operating clock...
Page 630 Response H'34 Size Number of areas Area-start address Area-last address ··· • Response, H'34, (one byte): Response to user boot MAT information inquiry • Size (one byte): The number of bytes that represents the number of areas, area-start addresses, and area-last address •...
Page 631 (i) Erased Block Information Inquiry The boot program will return the number of erased blocks and their addresses. Command H'26 • Command, H'26, (one byte): Inquiry regarding erased block information Response H'36 Size Number of blocks Block-start address Block-last address ···...
Page 632 Command H'3F Size Bit rate Input frequency Number of Multiplication Multiplication multiplication ratios ratio 1 ratio 2 • Command, H'3F, (one byte): Selection of new bit rate • Size (one byte): The number of bytes that represents the bit rate, input frequency, number of multiplication ratios, and multiplication ratio •...
Page 633 H'11: Checksum error H'24: Bit-rate selection error The rate is not available. H'25: Error in input frequency This input frequency is not within the specified range. H'26: Multiplication-ratio error The ratio does not match an available ratio. H'27: Operating frequency error The frequency is not within the specified range.
Page 634: Figure 20.22 New Bit-Rate Selection Sequence
When the new bit rate is selectable, the rate will be set in the register after sending ACK in response. The host will send an ACK with the new bit rate for confirmation and the boot program will response with that rate. Confirmation H'06 •...
Page 635 Error Response H'C0 H'51 • Error response, H'C0, (one byte): Error response for user boot MAT blank check • Error code, H'51, (one byte): Erasing error An error occurred and erasure was not completed. (7) Command Error A command error will occur when a command is undefined, the order of commands is incorrect, or a command is unacceptable.
Page 636: Table 20.12 Programming/Erasing Commands
(9) Programming/Erasing State A programming selection command makes the boot program select the programming method, a 128-byte programming command makes it program the memory with data, and an erasing selection command and block erasing command make it erase the block. The programming/erasing commands are listed below.
Page 637: Figure 20.23 Programming Sequence
Where the sequence of programming operations that is executed includes programming with another method or of another MAT, the procedure must be repeated from the programming selection command. The sequence for programming-selection and 128-byte programming commands is shown in figure 20.23. Host Boot program Programming selection (H'42, H'43, H'44)
Page 638 Command H'43 • Command, H'43, (one byte): User MAT programming selection Response H'06 • Response, H'06, (one byte): Response to user MAT programming selection When the programming program has been transferred, ACK will be returned. Error Response H'C3 ERROR • Error response: H'C3 (one byte): Error response to user MAT programming selection •...
Page 639 When there are less than 128 bytes of data to be programmed, the host should fill the rest with H'FF. Sending the 128-byte programming command with the address of H'FFFFFFFF will stop the programming operation. The boot program will interpret this as the end of the programming and wait for selection of programming or erasing.
Page 640: Figure 20.24 Erasure Sequence
Host Boot program Preparation for erasure (H'48) Transfer of erasure program Erasure (Erasure block number) Repeat Erasure Erasure (H'FF) Figure 20.24 Erasure Sequence (a) Erasure Selection The boot program will transfer the erasure program. User MAT data is erased by the transferred erasure program.
Page 641 Response H'06 • Response, H'06, (one byte): Response to erasure After erasure has been completed, ACK will be returned. Error Response H'D8 ERROR • Error response, H'D8, (one byte): Error response to erasure • ERROR (one byte): Error code H'11: Checksum error H'29: Block number error...
Page 642 • Read address (four bytes): Start address to be read from • Read size (four bytes): Size of data to be read • SUM (one byte): Checksum Response H'52 Read size Data ··· • Response: H'52 (one byte): Response to memory read •...
Page 643 Command H'4B • Command, H'4B, (one byte): Sum check for user MAT Response H'5B Size Checksum of MATs • Response, H'5B, (one byte): Response to the sum check of the user MAT • Size (one byte): The number of bytes that represents the checksum This is fixed to 4.
Page 644: Table 20.13 Status Codes
(16) Boot Program State Inquiry The boot program will return indications of its present state and error condition. This inquiry can be made in the inquiry/selection state or the programming/erasing state. Command H'4F • Command, H'4F, (one byte): Inquiry regarding boot program’s state Response H'5F Size...
Page 645: Table 20.14 Error Codes
Table 20.14 Error Codes Code Description H'00 No Error H'11 Checksum Error H'12 Program Size Error H'21 Device Code Mismatch Error H'22 Clock Mode Mismatch Error H'24 Bit Rate Selection Error H'25 Input Frequency Error H'26 Multiplication Ratio Error H'27 Operating Frequency Error H'29 Block Number Error...
Page 646: Usage Notes
20.9 Usage Notes 1. The initial state of the Renesas Technology product at its shipment is in the erased state. For the product whose revision of erasing is undefined, we recommend to execute automatic erasure for checking the initial state (erased state) and compensating.
Page 647 code area in programmer mode, a verification error will occur unless a countermeasure is taken for the PROM programmer and its program version. 12. The programming program that includes the initialization routine and the erasing program that includes the initialization routine are each 2 kbytes or less. Accordingly, when the CPU clock frequency is 20 MHz, the download for each program takes approximately TBD µs at the maximum.
Page 648 Rev. 1.00, 09/03, page 610 of 704...
Page 649: Section 21 Clock Pulse Generator
Section 21 Clock Pulse Generator This LSI incorporates a clock pulse generator which generates the system clock (φ) and internal clock. The clock pulse generator consists of an oscillator, duty adjustment circuit, and divider. Figure 21.1 shows a block diagram of the clock pulse generator. SCKCR SCK2 to SCK0 Duty...
Page 650: Register Description
21.1 Register Description The clock pulse generator has the following register. • System clock control register (SCKCR) 21.1.1 System Clock Control Register (SCKCR) SCKCR controls φ output and selects the division ratio for the divider. Bit Name Initial Value Description φ...
Page 651 Bit Name Initial Value Description SCK2 System Clock Select 2 to 0 SCK1 Select the division ratio. SCK0 000: 1/1 001: 1/2 010: 1/4 011: Setting prohibited 100: Setting prohibited 101: Setting prohibited 11x: Setting prohibited [Legend] x: Don’t care. Rev.
Page 652: Oscillator
21.2 Oscillator Clock pulses can be supplied either by connecting a crystal resonator or by providing external clock input. 21.2.1 Connecting Crystal Resonator Figure 21.2 shows a typical method of connecting a crystal resonator. An appropriate damping resistance R , given in table 21.1, should be used. An AT-cut parallel-resonance crystal resonator should be used.
Page 653: External Clock Input Method
21.2.2 External Clock Input Method Figure 21.4 shows a typical method of connecting an external clock signal. To leave the XTAL pin open, parasitic capacitance should be 10 pF or less. To input an inverted clock to the XTAL pin, the external clock should be set to high in standby mode.
Page 654: Figure 21.5 External Clock Input Timing
× 0.5 EXTAL Figure 21.5 External Clock Input Timing When a specified clock signal is input to the EXTAL pin, internal clock signal output is determined after the external clock output stabilization delay time (t ) has passed. As the clock DEXT signal output is not determined during the t cycle, a reset signal should be set to low to hold it...
Page 655: Duty Adjustment Circuit
21.3 Duty Adjustment Circuit The duty adjustment circuit is valid when the oscillation frequency is more than 5 MHz. This circuit adjusts the duty of the clock output by the oscillator and inputs it to the divider. 21.4 Divider The divider divides the clock output by the duty adjustment circuit, and generates the system clock (φ) of 1/1, 1/2, and 1/4.
Page 656: Notes On Operation Confirmation
21.5.3 Notes on Operation Confirmation Even if a crystal resonator is not connected to the EXTAL and XTAL pins or an external clock is not input, self-oscillation may occur at the several kHz frequency. Therefore, make sure that this LSI operates at the correct frequency. Rev.
Page 657: Section 22 Power-Down Modes
Section 22 Power-Down Modes In addition to the normal program execution state, this LSI has power-down modes in which operation of the CPU and oscillator is halted and power consumption is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip peripheral modules, and so on.
Page 658: Table 22.1 Operating Modes And Internal States Of Lsi
Table 22.1 Operating Modes and Internal States of LSI High- Clock Software Hardware Speed Division Sleep Module Standby Standby Operating State Mode Mode Mode Stop Mode Mode Mode Clock pulse generator Functions Functions Functions Functions Halted Halted Instruction Functions Functions Halted Functions Halted...
Page 659: Figure 22.1 Mode Transitions
Notes: Halted (Retained) in the table means that internal register values are retained and internal operations are suspended. Halted (Reset) in the table means that internal register values and internal states are initialized. In module stop mode, only modules for which a stop setting has been made are halted (reset or retained).
Page 660: Register Descriptions
22.1 Register Descriptions The registers relating to the power-down mode are shown below. For details on the system clock control register (SCKCR), refer to section 21.1.1, System Clock Control Register (SCKCR). • System clock control register (SCKCR) • Standby control register (SBYCR) •...
Page 661 Bit Name Initial Value Description 5 to 3   All 0 Reserved These bits are always read as 0. The initial value should not be changed. STS2 Standby Timer Select 2 to 0 STS1 Select the time the MCU waits for the clock to STS0 stabilize when software standby mode is cleared.
Page 662: Module Stop Control Registers H And L (Mstpcrh, Mstpcrl)
22.1.2 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL) MSTPCR performs module stop mode control. Setting a bit to 1, the corresponding module enters module stop mode, while clearing the bit to 0 clears the module stop mode. • MSTPCRH Bit Name Initial Value Module...
Page 663: Extension Module Stop Control Registers H And L
22.1.3 Extension Module Stop Control Registers H and L (EXMSTPCRH, EXMSTPCRL) EXMSTPCR performs module stop mode control. Setting a bit to 1, the corresponding module enters module stop mode, while clearing the bit to 0 clears the module stop mode. •...
Page 664: Operation
22.2 Operation 22.2.1 Clock Division Mode When the SCK2 to SCK0 bits in SCKCR are set to a value from B'001 to B'010, a transition is made to clock division mode. In clock division mode, the CPU and on-chip peripheral functions all operate on the operating clock (1/2 or 1/4) specified by bits SCK2 to SCK0.
Page 665: Software Standby Mode
• Exiting Sleep Mode by STBY Pin When the STBY pin level is driven low, a transition is made to hardware standby mode. 22.2.3 Software Standby Mode Transition to Software Standby Mode: If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, software standby mode is entered.
Page 666: Table 22.2 Oscillation Stabilization Time Settings
Setting Oscillation Stabilization Time after Clearing Software Standby Mode: Bits STS2 to STS0 in SBYCR should be set as described below. • Using Crystal Resonator Set bits STS2 to STS0 so that the standby time is more than the oscillation stabilization time. Table 22.2 shows the standby times for operating frequencies and settings of bits STS2 to STS0.
Page 667: Figure 22.2 Software Standby Mode Application Example
Software Standby Mode Application Example: Figure 22.2 shows an example in which a transition is made to software standby mode at the falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI pin.
Page 668: Hardware Standby Mode
22.2.4 Hardware Standby Mode Transition to Hardware Standby Mode: When the STBY pin is driven low, a transition is made to hardware standby mode from any mode. In hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power consumption.
Page 669: Module Stop Mode
Oscillator Oscillation Reset stabilization exception time handling Figure 22.3 Hardware Standby Mode Timing 22.2.5 Module Stop Mode Module stop mode can be set for individual on-chip peripheral modules. When the corresponding MSTP bit in MSTPCR or EXMSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode.
Page 670: Table 22.3 Φ Pin State In Each Processing State
Table 22.3 φ φ φ φ Pin State in Each Processing State Register Setting Normal Operating Software Standby Hardware State Sleep Mode Mode Standby Mode PSTOP High impedance High impedance High impedance High impedance φ output φ output Fixed high High impedance Fixed high Fixed high...
Page 671: Usage Notes
22.4 Usage Notes 22.4.1 I/O Port State In software standby mode, I/O port states are retained. Therefore, there is no reduction in current consumption for the output current when a high-level signal is output. 22.4.2 Current Consumption during Oscillation Stabilization Standby Period Current consumption increases during the oscillation stabilization standby period.
Page 672 Rev. 1.00, 09/03, page 634 of 704...
Page 673: Section 23 List Of Registers
Section 23 List of Registers The register list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. Register Addresses (Address Order) •...
Page 674: Register Addresses (Address Order)
23.1 Register Addresses (Address Order) The data bus width indicates the numbers of bits by which the register is accessed. The number of access states indicates the number of states based on the specified reference clock. Number of Number Data Bus Access Register Name Abbreviation...
Page 675 Number of Number Data Bus Access Register Name Abbreviation of Bits Address Module Width States Transmit data register_1 TDR_1 H'FDBB SCI_1 Serial status register_1 SSR_1 H'FDBC SCI_1 Receive data register_1 RDR_1 H'FDBD SCI_1 Serial interface mode register_1 SCMR_1 H'FDBE SCI_1 Serial mode register_2 SMR_2 H'FDC0...
Page 676 Number of Number Data Bus Access Register Name Abbreviation of Bits Address Module Width States A/D data register F ADDRF H'FDEA A/D data register G ADDRG H'FDEC A/D data register H ADDRH H'FDEE A/D control/status register ADCSR H'FDF0 A/D control register ADCR H'FDF1 Input capture register...
Page 677 Number of Number Data Bus Access Register Name Abbreviation of Bits Address Module Width States Input capture register F_0 TICRF_0 H'FE13 TMRX_0 Timer counter X_0 TCNTX_0 H'FE14 TMRX_0 Time constant register C_0 TCORC_0 H'FE15 TMRX_0 Timer constant register AX_0 TCORAX_0 H'FE16 TMRX_0 Timer constant register BX_0...
Page 678 Number of Number Data Bus Access Register Name Abbreviation of Bits Address Module Width States Timer control register_1 FR_TCR_1* H'FE36 FRT_1 Timer output compare control TOCR_1 H'FE37 FRT_1 register_1 Input capture register A_1 ICRA_1 H'FE38 FRT_1 Output compare register AR_1 OCRAR_1 H'FE38 FRT_1...
Page 679 Number of Number Data Bus Access Register Name Abbreviation of Bits Address Module Width States Edge sense register_1 SEDGR_1 H'FE57 Timer connection_1 Timer control register Y_1 TCRY_1 H'FE58 TMRY_1 Timer control/status register Y_1 TCSRY_1 H'FE59 TMRY_1 Time constant register AY_1 TCORAY_1 H'FE5A TMRY_1...
Page 680 Number of Number Data Bus Access Register Name Abbreviation of Bits Address Module Width States Port register 4 PORT4 H'FEC4 PORT Port register 5 PORT5 H'FEC5 PORT Port register 6 PORT6 H'FEC6 PORT Port register 7 PORT7 H'FEC7 PORT Port register 8 PORT8 H'FEC8 PORT...
Page 681 Number of Number Data Bus Access Register Name Abbreviation of Bits Address Module Width States Port 3 pull-up MOS control register P3PCR H'FEF2 PORT Port 6 pull-up MOS control register P6PCR H'FEF3 PORT Port 6 open-drain control register P6ODR H'FEF4 PORT Port function control register PFCR...
Page 682 Number of Number Data Bus Access Register Name Abbreviation of Bits Address Module Width States C bus control register B_2 ICCRB_2 H'FF99 IIC3_2 C bus mode register_2 ICMR_2 H'FF9A IIC3_2 C bus interrupt enable register_2 ICIER_2 H'FF9B IIC3_2 C bus status register_2 ICSR_2 H'FF9C IIC3_2...
Page 683 Number of Number Data Bus Access Register Name Abbreviation of Bits Address Module Width States Timer control/status register TCSR H'FFBC (Read) Peripheral clock select register PCSR H'FFC0 PWM output enable register PWOER H'FFC3 PWM data polarity register PWDPR H'FFC5 PWM register select PWSL H'FFC6 PWM data registers 7 to 0...
Page 684 Number of Number Data Bus Access Register Name Abbreviation of Bits Address Module Width States Timer counter_1 TCNT_1 H'FFE6 TPU_1 Timer general register A_1 TGRA_1 H'FFE8 TPU_1 Timer general register B_1 TGRB_1 H'FFEA TPU_1 Timer control register_2 TCR_2 H'FFF0 TPU_2 Timer mode register_2 TMDR_2 H'FFF1...
Page 685: Register Bits
23.2 Register Bits Register addresses and bit names of the on-chip peripheral modules are described below. Each line covers eight bits, so 16-bit registers are shown as 2 lines. Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0...
Page 686 Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module SMR_0 STOP CKS1 CKS0 SCI_0 BRR_0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SCR_0 MPIE TEIE CKE1 CKE0 TDR_0 bit7 bit6 bit5 bit4...
Page 687 Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module RDR_4 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SCI_4       SCMR_4 SDIR SINV ADDRA converter ...
Page 688 Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module OCRB_0 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 FRT_0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 FR_TCR_0* IEDGA IEDGB IEDGC IEDGD BUFEA...
Page 689 Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TCORB1_0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 TMR01_0 TCNT0_0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 TCNT1_0 bit7 bit6 bit5 bit4...
Page 690 Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module OCRDM_1 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 FRT_1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ICRD_1 bit15 bit14 bit13 bit12 bit11...
Page 691 Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module     FCCS FLER WEINTE Flash memory        FPCS PPVS    ...
Page 692 Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module P1DR P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR Port P2DR P27DR P26DR P25DR P24DR P23DR P22DR P21DR P20DR P3DR P37DR P36DR P35DR P34DR...
Page 693 Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ICCRA_0 RCVD CKS3 CKS2 CKS1 CKS0 IIC3_0    ICCRB_0 BBSY SDAO SCLO IICRST    ICMR_0 WAIT BCWP ICIER_0 TEIE NAKIE...
Page 694 Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ICCRA_3 RCVD CKS3 CKS2 CKS1 CKS0 IIC3_3    ICCRB_3 BBSY SDAO SCLO IICRST    ICMR_3 WAIT BCWP ICIER_3 TEIE NAKIE...
Page 695 Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module DACNTH PWMX  DACNTL UC10 UC11 UC12 UC13 REGS      TSTR CST2 CST1 CST0 common   ...
Page 696 Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module  TCR_2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_2     TMDR_2 TIOR_2 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0...
Page 697: Register States In Each Operating Mode
23.3 Register States in Each Operating Mode Register Software Hardware Abbreviation Standby Standby Reset High-Speed Sleep Module Stop Module     IPRA Initialized Initialized Interrupt     IPRB Initialized Initialized     IPRC Initialized Initialized ...
Page 698 Register Software Hardware Abbreviation Reset High-Speed Sleep Module Stop Standby Standby Module     SMR_2 Initialized Initialized SCI_2     BRR_2 Initialized Initialized     SCR_2 Initialized Initialized   TDR_2 Initialized Initialized Initialized Initialized ...
Page 699 Register Software Hardware Abbreviation Reset High-Speed Sleep Module Stop Standby Standby Module     TWICR Initialized Initialized Duty measurement     TWCNT Initialized Initialized circuit     TWCR1 Initialized Initialized     TWCR2 Initialized Initialized...
Page 700 Register Software Hardware Abbreviation Reset High-Speed Sleep Module Stop Standby Standby Module     TCORB0_0 Initialized Initialized TMR01_0     TCORB1_0 Initialized Initialized     TCNT0_0 Initialized Initialized     TCNT1_0 Initialized Initialized ...
Page 701 Register Software Hardware Abbreviation Reset High-Speed Sleep Module Stop Standby Standby Module     TCORAX_1 Initialized Initialized TMRX_1     TCORBX_1 Initialized Initialized     TCR0_1 Initialized Initialized TMR01_1     TCR1_1 Initialized Initialized ...
Page 702 Register Software Hardware Abbreviation Reset High-Speed Sleep Module Stop Standby Standby Module     MSTPCRH Initialized Initialized System     MSTPCRL Initialized Initialized     EXMSTPCRH Initialized Initialized     EXMSTPCRL Initialized Initialized ...
Page 703 Register Software Hardware Abbreviation Reset High-Speed Sleep Module Stop Standby Standby Module     P5DDR Initialized Initialized Port     P6DDR Initialized Initialized     P8DDR Initialized Initialized     P9DDR Initialized Initialized ...
Page 704 Register Software Hardware Abbreviation Reset High-Speed Sleep Module Stop Standby Standby Module     ICSRA_0 Initialized Initialized IIC3_0     SARA_0 Initialized Initialized     SARB_0 Initialized Initialized     SAMR_0 Initialized Initialized ...
Page 705 Register Software Hardware Abbreviation Reset High-Speed Sleep Module Stop Standby Standby Module     Initialized Initialized     BCRA1 Initialized Initialized     BCRA2 Initialized Initialized     BCRA3 Initialized Initialized  ...
Page 706 Register Software Hardware Abbreviation Reset High-Speed Sleep Module Stop Standby Standby Module     TCR_1 Initialized Initialized TPU_1     TMDR_1 Initialized Initialized     TIOR_1 Initialized Initialized     TIER_1 Initialized Initialized ...
Page 707: Section 24 Electrical Characteristics
Section 24 Electrical Characteristics 24.1 Absolute Maximum Ratings Table 24.1 lists the absolute maximum ratings. Table 24.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage* –0.3 to +4.3 Power supply voltage (VCL pin) –0.3 to +4.3 Input voltage (except ports 0 and 7) –0.3 to V +0.3 Input voltage (ports 0 and 7)
Page 708: Dc Characteristics
24.2 DC Characteristics Table 24.2 lists the DC characteristics. Table 24.3 lists the permissible output currents. Table 24.2 DC Characteristics Conditions: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, = 3.0 V to AV = AV = 0 V Item...
Page 709 Item Symbol Min. Typ. Max. Unit Test Conditions – 0.5   Output high All output pins (except for = –200 µA voltage P80 to P83, PC0 to PC3) – 1.0   = –1 mA   P80 to P83, PC0 to PC3* = –200 µA ...
Page 710: Figure 24.1 Darlington Transistor Drive Circuit (Example)
Notes: 1. Do not leave the AVCC, AVref, and AVSS pins open even if the A/D converter is not used. Even if the A/D converter is not used, apply a value in the range from 3.0 V to 3.6 V to the AVCC and AVref pins by connection to the power supply (VCC).
Page 711: Ac Characteristics
24.3 AC Characteristics Figure 24.2 shows the test conditions for the AC characteristics. LSI output pin IOL = 1.6 A, IOH = 200 A I/O reference level: 1.5 V VT = 1.5 V CL = 30 pF (The CL value includes capacitance of measuring jigs.) Figure 24.2 Output Load Circuit 24.3.1 Clock Timing...
Page 712: Figure 24.3 System Clock Timing
Table 24.4 Clock Timing = 0 V, φ = 5 MHz to 20 MHz Condition: = 3.0 V to 3.6 V, V Item Symbol Min. Max. Unit Reference Clock cycle time Figure 24.3  Clock high pulse width  Clock low pulse width ...
Page 713: Control Signal Timing
φ ( i = 0 to 7 ) OSC2 Figure 24.5 Oscillation Stabilization Timing (Exiting Software Standby Mode) 24.3.2 Control Signal Timing Table 24.5 shows the control signal timing. Table 24.5 Control Signal Timing = 0 V, φ = 5 MHz to 20 MHz Condition: = 3.0 V to 3.6 V, V Test...
Page 714: Figure 24.6 Reset Input Timing
RESS RESS RESW Figure 24.6 Reset Input Timing φ NMIS NMIH NMIW ( i = 0 to 7 )* IRQW IRQS IRQH (edge input) IRQS (level input) Note: * To cancel software standby mode, SSIER should be set. Figure 24.7 Interrupt Input Timing Rev.
Page 715: Bus Timing
24.3.3 Bus Timing Table 24.6 shows the bus timing. Table 24.6 Bus Timing (Normal Extension) = 0 V, φ = 5 MHz to 20 MHz Condition: = 3.0 V to 3.6 V, V Item Symbol Min. Max. Unit Test Conditions ...
Page 716: Figure 24.8 Basic Bus Timing/2-State Access
φ A15 to A0, RSD2 RSD1 ACC2 (Read) ACC3 D15 to D0 (Read) WRD2 WRD2 (Write) WSW1 D15 to D0 (Write) Figure 24.8 Basic Bus Timing/2-State Access Rev. 1.00, 09/03, page 678 of 704...
Page 717: Figure 24.9 Basic Bus Timing/3-State Access
φ A15 to A0, RSD1 RSD2 ACC4 (Read) ACC5 D15 to D0 (Read) WRD1 WRD2 (Write) WSW2 D15 to D0 (Write) Figure 24.9 Basic Bus Timing/3-State Access Rev. 1.00, 09/03, page 679 of 704...
Page 718: Figure 24.10 Basic Bus Timing/3-State Access With One Wait State
φ A15 to A0 (Read) D15 to D0 (Read) (Write) D15 to D0 (Write) Figure 24.10 Basic Bus Timing/3-State Access with One Wait State Rev. 1.00, 09/03, page 680 of 704...
Page 719: Table 24.7 Bus Timing (Multiplex Extension)
Table 24.7 Bus Timing (Multiplex Extension) Item Symbol Min. Max. Unit Test Conditions  Address delay time Figures 24.11 to 24.13  Address setup time 2 0.5 x t –15  Address hold time 2 1.0 x t – 10 ...
Page 720: Figure 24.11 Muliplex Bus Timing/2-State Access
RSD1 ACC2 RSD2 ACC6 AD15 to AD0 A15 to A0 D15 to D0 WRD2 WRD2 WSW1 AD15 to AD0 A15 to A0 D15 to D0 Figure 24.11 Muliplex Bus Timing/2-State Access Rev. 1.00, 09/03, page 682 of 704...
Page 721: Figure 24.12 Multiplex Bus Timing/3-State Access
RSD1 ACC4 RSD2 ACC6 AD15 to AD0 A15 to A0 D15 to D0 WRD1 WRD2 WSW2 AD15 to AD0 A15 to A0 D15 to D0 Figure 24.12 Multiplex Bus Timing/3-State Access Rev. 1.00, 09/03, page 683 of 704...
Page 722: Figure 24.13 Multiplex Bus Timing/3-State Access With One Wait State
T DOW (Read) AD15 to AD0 (Read) (Write) AD15 to AD0 (Write) Figure 24.13 Multiplex Bus Timing/3-State Access with One Wait State Rev. 1.00, 09/03, page 684 of 704...
Page 723: Timing Of On-Chip Peripheral Modules
24.3.4 Timing of On-Chip Peripheral Modules Tables 24.8 to 24.10 show the on-chip peripheral module timing. Table 24.8 Timing of On-Chip Peripheral Modules = 0 V, φ = 5 MHz to 20 MHz Condition: = 3.0 V to 3.6 V, V Item Symbol Min.
Page 724: Figure 24.14 I/O Port Input/Output Timing
φ Ports 0 to 9, and A to C (read) Ports 1 to 6, 8, 9, and A to C (write) Figure 24.14 I/O Port Input/Output Timing φ FTOD FTOA_0, FTOB_0, FTOA_1, FTOB_1 FTIS FTIA_0, FTIB_0, FTIC_0, FTID_0, FTIA_1, FTIB_1, FTIC_1, FTID_1 Figure 24.15 FRT Input/Output Timing φ...
Page 725: Figure 24.17 Tpu Input/Output Timing
TOCD Output compare output* TICS Input capture input* Note: * TIOCA0 to TIOCA2, TIOCB0 to TIOCB2, TIOCC0, TIOCD0, ExTIOCA0 to ExTIOCA2, ExTIOCB0 to ExTIOCB2, ExTIOCC0, ExTIOCD0 Figure 24.17 TPU Input/Output Timing TCKS TCKS TCLKA to TCLKD ExTCLKA to ExTCLKD TCKWL TCKWH Figure 24.18 TPU Clock Input Timing φ...
Page 726: Figure 24.21 8-Bit Timer Reset Input Timing
φ TMRS TMI0_0, TMI1_0, TMIX_0, TMIY_0, TMI0_1, TMI1_1, TMIX_1, TMIY_1 Figure 24.21 8-Bit Timer Reset Input Timing φ PWOD PW7 to PW0, EXPW7 to EXPW0, PWX1, PWX0 Figure 24.22 PWM, PWMX Output Timing SCKW SCKr SCKf SCK0 to SCK4 Scyc Figure 24.23 SCK Clock Input Timing SCK0 to SCK4 TxD0 to TxD4...
Page 727: Figure 24.25 A/D Converter External Trigger Input Timing
TRGS Figure 24.25 A/D Converter External Trigger Input Timing Table 24.9 I C Bus Interface Timing = 3.0 to 3.6 V, V = 0.0 V, T = –20 to +75°C, unless otherwise indicated. Values Test Reference Item Symbol Condition Min. Typ.
Page 728: Figure 24.26 Input/Output Timing Of I
SDA0 SDA5 SCLH STOS STAH STAS SCL0 SCL5 SCLL SDAS SDAH Note: * S, P, and Sr indicate the following conditions: S: Start condition P: Stop condition Sr: Retransmission start condition Figure 24.26 Input/Output Timing of I C Bus Interface 3 Rev.
Page 729: A/D Conversion Characteristics
24.4 A/D Conversion Characteristics Table 24.10 lists the A/D conversion characteristics. Table 24.10 A/D Conversion Characteristics (AN15 to AN0 Input: 134/266-State Conversion) Condition: = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, AV = 3.0 V to AVCC, = 0 V, φ...
Page 730: Flash Memory Characteristics
24.5 Flash Memory Characteristics Table 24.11 lists the flash memory characteristics. Table 24.11 Flash Memory Characteristics Condition: = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, AVref = 3.0 V to AV = AV = 0 V, Ta = 0°C to +75°C (operating temperature range for programming/erasing) Item Symbol Min.
Page 731: Usage Notes
24.6 Usage Notes It is necessary to connect a capacitor between the VCL pin and VSS pin for stable internal voltage. An example of connection is shown in figure 24.27. External capacitor for power stabilization 0.1 µF or 0.47 µF Do not connect Vcc power supply to the VCL pin.
Page 732 Rev. 1.00, 09/03, page 694 of 704...
Page 733: Appendix
Appendix I/O Port States in Each Pin State Table A.1 I/O Port States in Each Pin State Port Name MCU Operating Hardware Standby Software Standby Sleep Pin Name Mode Reset Mode Mode Mode Program Execution State Port 0 (EXPE = 1) Kept Kept Input port...
Page 734 Port Name MCU Operating Hardware Software Standby Sleep Pin Name Mode Reset Standby Mode Mode Mode Program Execution State AS/AH, HWR/RD Ports 95 to 93 (EXPE = 1) AS, AH, HWR, (EXPE = 0) Kept Kept I/O port Ports 92 and 91 (EXPE = 1) Kept Kept I/O port...
Page 735: Product Lineup
Product Lineup Product Type Type Code Mark Code Package (Code) H8S/2437 F-ZTAT version HD64F2437F DF2437F 128-pin QFP (FP-128B) H8S/2437 F-ZTAT version HD64F2437FV* DF2437FV 128-pin QFP (FP-128B) Note: * Pb-free version Rev. 1.00, 09/03, page 697 of 704...
Page 736: Package Dimensions
Package Dimensions For package dimensions, dimensions described in Renesas Semiconductor Packages have priority. 22.0 ± 0.2 Unit: mm 0.22 ± 0.05 0.10 M 0.20 ± 0.04 0.75 0.75 0˚ – 8˚ 0.5 ± 0.2 0.10 Package Code FP-128B JEDEC —...
Page 737: Index
Index 14-Bit PWM Timer (PWMX)....225 BRR ........ 436, 636, 648, 659 16-Bit Count Mode ......... 287 Buffer Operation ........334 16-Bit Free-Running Timer (FRT) ..239 Carrier frequency ........219 16-Bit Timer Pulse Unit (TPU)....299 Cascaded Connection ......287 16-Bit, 2-State Access Space ....107 Cascaded Operation ........337 16-Bit, 3-State Access Space ....
Page 738 Reset exception handling ..... 59 ICIB ............260 Stack Status after Exception Handling ICIC ............260 .............. 63 ICID ............260 Traces ........... 61 ICIER ......483, 643, 655, 665 Trap Instruction ........62 ICIX ............291 Exception Vector Table ......58 ICMR ......
Page 739 MSTPCR ......624, 641, 653, 664 P8DR....... 184, 642, 654, 664 Multiply-Accumulate Register P9DDR......189, 642, 654, 665 (MAC) ............27 P9DR....... 190, 642, 654, 664 Multiprocessor Communication Function parity error ..........449 ..............453 PCSR....... 231, 645, 656, 667 NMI ............89 Periodic count operation ......328 NMI Interrupt..........
Page 740: Section 13 Timer Connection
Register indirect with post- TCONRS......375, 639, 651, 662 increment ..........44 TCORA......273, 639, 650, 661 Reset ............59 TCORB ......273, 639, 650, 661 Resolution..........219 TCORC ......282, 639, 650, 661 RRRMDCR ..........52 TCR......248, 305, 638, 650, 661 RRRSYSCR..........
Page 741 user memory MAT........525 Watchdog Timer Mode ......420 User Program Mode........ 555 Waveform Output by Compare Match..329 VSYNCO Output........397 WOVI............422 Watchdog Timer (WDT) ......417 Rev. 1.00, 09/03, page 703 of 704...
Page 742 Rev. 1.00, 09/03, page 704 of 704...
Page 743 H8S/2437 Group Hardware Manual Publication Date: Rev.1.00, September 19, 2003 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Technical Documentation & Information Department Renesas Kodaira Semiconductor Co., Ltd. 2003 Renesas Technology Corp. All rights reserved. Printed in Japan.
Page 744 Dornacher Str. 3, D-85622 Feldkirchen, Germany Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11 Renesas Technology Hong Kong Ltd. 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2375-6836 Renesas Technology Taiwan Co., Ltd.
Page 746 H8S/2437 Group Hardware Manual REJ09B0059-0100Z...

Renesas H8S/2437 Hardware Manual

Section 1 Overview

Section 5 Interrupt Controller

Section 1 Overview

Section 2 CPU

Section 3 MCU Operating Modes

Section 3 MCU Operating Modes

Section 4 Exception Handling

Section 4 Exception Handling

Section 5 Interrupt Controller

Section 6 Bus Controller (BSC)

Section 6 Bus Controller (BSC)

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