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Section 10 16-Bit Free-Running Timer (FRT)
10.3.6
Automatic Addition Timing
When the OCRAMS bit in TOCR is set to 1, the contents of OCRAR and OCRAF are
automatically added to OCRA alternately, and when an OCRA compare-match occurs, a write to
OCRA is performed. Figure 10.7 shows the OCRA write timing.
φ
FRC
OCRA
OCRAR, OCRAF
Compare-match
signal
10.4
Interrupt Sources
The free-running timer can request three interrupts: OCIA, OCIB, and FOVI. Each interrupt can
be enabled or disabled by an enable bit in TIER. Independent signals are sent to the interrupt
controller for each interrupt. Table 10.1 lists the sources and priorities of these interrupts.
The OCIA and OCIB interrupts can be used as the on-chip DTC activation sources.
Table 10.1 FRT Interrupt Sources
Interrupt
Interrupt Source
OCIA
Compare match of OCRA OCFA
OCIB
Compare match of OCRB OCFB
FOVI
Overflow of FRC
Rev. 1.00 Mar. 12, 2008 Page 384 of 1178
REJ09B0403-0100
N
N
A
Figure 10.7 OCRA Automatic Addition Timing
Interrupt Flag
DTC Activation
Possible
Possible
OVF
Not possible
N +1
N + A
Priority
High
Low
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