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17.3.5
SS Status Register (SSSR)
SSSR is a status flag register for interrupts.
Bit
Bit Name
7
6
ORER
5, 4
3
TEND
Initial
Value
R/W
0
0
R/W
All 0
R/W
1
R
Section 17 Synchronous Serial Communication Unit (SSU)
Description
Reserved
This bit is always read as 0. The initial value should not
be changed.
Overrun Error
If the next data is received while RDRF = 1, an overrun
error occurs, indicating abnormal termination. SSRDR
stores 1-frame receive data before an overrun error
occurs and loses data to be received later. While ORER
= 1, consecutive serial reception cannot be continued.
Serial transmission cannot be continued, either.
[Setting condition]
When one byte of the next reception is completed with
RDRF = 1
[Clearing condition]
When writing 0 after reading ORER = 1
Reserved
These bits are always read as 0. The initial value
should not be changed.
Transmit End
[Setting condition]
•
When the last bit of transmit data is transmitted
while the TENDSTS bit in SSCR2 is cleared to 0
and the TDRE bit is set to 1
•
After the last bit of transmit data is transmitted while
the TENDSTS bit in SSCR2 is set to 1 and the
TDRE bit is set to 1
[Clearing conditions]
•
When writing 0 after reading TEND = 1
•
When writing data to SSTDR
Rev. 1.00 Mar. 12, 2008 Page 559 of 1178
REJ09B0403-0100
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