Immediate#Xx:8, #Xx:16, Or #Xx:32 - Renesas H8S Family Hardware Manual

Table 2.12 Absolute Address Access Ranges

Absolute Address

Data address

Program instruction

Note: Normal mode is not available in this LSI.

Immediate#xx:8, #xx:16, or #xx:32

The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an

The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit

manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit

number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a

vector address.

Program-Counter Relative@(d:8, PC) or @(d:16, PC)

This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in

the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address.

Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0

(H'00). The PC value to which the displacement is added is the address of the first byte of the next

instruction, so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to

+32768 bytes (–16383 to +16384 words) from the branch instruction. The resulting value should

be an even number.

Normal Mode*

8 bits (@aa:8)

H'FF00 to H'FFFF

16 bits (@aa:16)

H'0000 to H'FFFF

32 bits (@aa:32)

24 bits (@aa:24)

Advanced Mode

H'FFFF00 to H'FFFFFF

H'000000 to H'007FFF,

H'FF8000 to H'FFFFFF

H'000000 to H'FFFFFF

Rev. 1.00 Mar. 12, 2008 Page 53 of 1178

REJ09B0403-0100

Section 2 CPU