Bit Rate Setting Register (Ecbrr) - Renesas H8S Family Hardware Manual

21.2.18 Bit Rate Setting Register (ECBRR)

ECBRR sets the bit rate for retransmission and reception.
Bit Bit Name

7 to 1
0 RTM
21.2.19 Transmit Interrupt Register (TRIMD)
TRIMD is a 32-bit readable/writable register that specifies whether or not to notify write-back
completion for each frame using the TWB bit in EESR and an interrupt on transmit operations.
Bit Bit Name

31 to 1
0 TIS
Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Initial
Value R/W Description
All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
0 R/W Transmit/Receive Rate
0: 10 Mbps
1: 100 Mbps
Initial
Value R/W Description
All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
0 R/W Transmit Interrupt Setting
0: Write-back completion for each frame is not
1: Write-back completion for each frame using the
notified
TWB bit in EESR is notified
Rev. 1.00 Mar. 12, 2008 Page 815 of 1178
REJ09B0403-0100