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10.2.6
Timer Control Register (TCR)
TCR selects the rising or falling edge of the input capture signals, enables the input capture buffer
mode, and selects the FRC clock source.
Bit
Bit Name
7 to 2
1
CKS1
0
CKS0
Initial
Value
R/W
Description
All 0
R
Reserved
These bits are always read as 0 and cannot be modified.
0
R/W
Clock Select 1 and 0
0
R/W
Select clock source for FRC.
00: φ/2 internal clock source
01: φ/8 internal clock source
10: φ/32 internal clock source
11: Reserved
Section 10 16-Bit Free-Running Timer (FRT)
Rev. 1.00 Mar. 12, 2008 Page 379 of 1178
REJ09B0403-0100
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