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Table 19.3 Host Register Selection
Bits 15 to 3
LADR1 (bits 15 to 3) 0
LADR1 (bits 15 to 3) 1
LADR1 (bits 15 to 3) 0
LADR1 (bits 15 to 3) 1
LADR2 (bits 15 to 3) 0
LADR2 (bits 15 to 3) 1
LADR2 (bits 15 to 3) 0
LADR2 (bits 15 to 3) 1
Table 19.4 Slave Selection Internal Registers
Slave (R/W) Bus Width (B/W) LADR12SEL
R/W
B
R/W
B
R/W
B
R/W
B
R/W
W
R/W
W
I/O Address
Bit 2 Bit 1
LADR1 (bit 1) LADR1 (bit 0) I/O write
LADR1 (bit 1) LADR1 (bit 0) I/O write
LADR1 (bit 1) LADR1 (bit 0) I/O read
LADR1 (bit 1) LADR1 (bit 0) I/O read
LADR2 (bit 1) LADR2 (bit 0) I/O write
LADR2 (bit 1) LADR2 (bit 0) I/O write
LADR2 (bit 1) LADR2 (bit 0) I/O read
LADR2 (bit 1) LADR2 (bit 0) I/O read
0
1
0
1
0
1
Transfer
Bit 0
Cycle
LADR12
LADR12H
LADR12H
LADR12L
LADR12L
LADR12H
LADR12L
LADR12H
LADR12L
Rev. 1.00 Mar. 12, 2008 Page 685 of 1178
Section 19 LPC Interface (LPC)
Host Register Selection
IDR1 write (data),
C/D1 ← 0
IDR1 write (command),
C/D1 ← 1
ORD1 read
STR1 read
IDR2 write (data),
C/D2 ← 0
IDR2 write (command),
C/D2 ← 1
ODR2 read
STR2 read
Internal Register
LADR1H
LADR2H
LADR1L
LADR2L
LADR1H
LADR1L
LADR2H
LADR2L
REJ09B0403-0100
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