Renesas H8S Family Hardware Manual page 341

∆t
Latch
Pin input
Sampling clock
P4n input
1 expected
P4nDR
0 expected
P4nDR
(n = 7 to 4)
φ/2, φ/32, φ/512, φ/8192,
φ/32768, φ/65536,
φ/131072, φ/262144
Sampling clock selection
Latch Latch
Figure 8.9 Noise Canceler Circuit
Figure 8.10 Noise Canceler Operation
Section 8 I/O Ports
Match
detection
circuit
Rev. 1.00 Mar. 12, 2008 Page 293 of 1178
Port data
register
REJ09B0403-0100