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Renesas H8S Family Hardware Manual page 627

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Start
[1]
Initial setting
TE = 1 (transmission enabled)
[2]
Read TDRE in SSSR
TDRE = 1?
Yes
Write transmit data to SSTDR
TDRE automatically cleared
Data transferred from SSTDR to SSTRSR
Set TDRE to 1 to start transmission
[3]
Consecutive data transmission?
No
Read TEND in SSSR
TEND = 1?
Yes
Clear TEND to 0
Confirm that TEND is cleared to 0
One bit time
[4]
quantum elapsed?
Yes
Clear TE in SSER to 0
End transmission
Figure 17.14 Flowchart Example of Transmission Operation
Section 17 Synchronous Serial Communication Unit (SSU)
[4][1] Initial setting:
[2] Check that the SSU state and write transmit data:
[3] Procedure for consecutive data transmission:
No
[4] Procedure for data transmission end:
Yes
No
No
Note: Hatching boxes represent SSU internal operations.
(Clock Synchronous Communication Mode)
Specify the transmit data format.
Write transmit data to SSTDR after reading and confirming
that the TDRE bit is 1. The TDRE bit is automatically cleared
to 0 and transmission is started by writing data to SSTDR.
To continue data transmission, confirm that the TDRE bit is 1
meaning that SSTDR is ready to be written to. After that, data
can be written to SSTDR. The TDRE bit is automatically
cleared to 0 by writing data to SSTDR.
To end data transmission, confirm that the TEND bit is cleared
to 0. After completion of transmitting the last bit, clear the TE
bit to 0.
Rev. 1.00 Mar. 12, 2008 Page 579 of 1178
REJ09B0403-0100

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R4f2472R4f2462H8s/2462H8s/2400 seriesH8s/2472