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Section 19 LPC Interface (LPC)
Initial
Bit
Bit Name
Value
4
FGA20E
0
3
SDWNE
0
Rev. 1.00 Mar. 12, 2008 Page 672 of 1178
REJ09B0403-0100
R/W
Slave Host Description
R/W
Fast Gate A20 Function Enable
Enables or disables the fast Gate A20 function. The
PD3DDR bit should be cleared to 0 when the LPC is
used. With the fast Gate A20 disabled, the normal
Gate A20 can be implemented by firmware controlling
PD3 output.
0: Fast Gate A20 function disabled
General I/O function of pin PD3 is enabled
The internal state of GA20 output is initialized to 1
1: Fast Gate A20 function enabled
GA20 pin output is open-drain (external pull-up
resistor (Vcc) required)
R/W
LPC Software Shutdown Enable
Controls LPC interface shutdown. For details of the
LPC shutdown function, and the scope of initialization
by an LPC reset and an LPC shutdown, see section
19.4.6, LPC Interface Shutdown Function (LPCPD).
0: Normal state, LPC software shutdown setting
enabled
[Clearing conditions]
•
Writing 0
•
LPC hardware reset or LPC software reset
•
LPC hardware shutdown release (rising edge of
LPCPD signal)
1: LPC hardware shutdown state setting enabled
Hardware shutdown state when LPCPD signal is
low level
[Setting condition]
Writing 1 after reading SDWNE = 0
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