Basic Operation Timing In Address-Data Multiplex Extended Mode - Renesas H8S Family Hardware Manual

Section 6 Bus Controller (BSC)
6.5.5

Basic Operation Timing in Address-Data Multiplex Extended Mode

(1) 8-Bit, 2-State Data Access Space
Figures 6.16 and 6.17 show the bus timing for an 8-bit, 2-state access space. When an 8-bit access
space is accessed, the lower half (AD7 to AD0) of the data bus is used. Wait states cannot be
inserted.
CS256
IOS
AH
RD
HWR
AD7 to AD0
Figure 6.16 Bus Timing for 8-Bit, 2-State Access Space
Rev. 1.00 Mar. 12, 2008 Page 140 of 1178
REJ09B0403-0100
Read Cycle
Address
T T T
1 AW 2
φ
Address
Write Cycle
Data Address
T T T T T
3 4 1 AW
Data Address
Data
T T
2 3 4
Data