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10.2
Register Descriptions
The FRT has the following registers.
• Free-running counter (FRC)
• Output compare register A (OCRA)
• Output compare register B (OCRB)
• Output compare register AR (OCRAR)
• Output compare register AF (OCRAF)
• Timer interrupt enable register (TIER)
• Timer control/status register (TCSR)
• Timer control register (TCR)
• Timer output compare control register (TOCR)
Note: OCRA and OCRB share the same address. Register selection is controlled by the OCRS
bit in TOCR.
10.2.1
Free-Running Counter (FRC)
FRC is a 16-bit readable/writable up-counter. The clock source is selected by bits CKS1 and
CKS0 in TCR. FRC can be cleared by compare-match A. When FRC overflows from H'FFFF to
H'0000, the overflow flag bit (OVF) in TCSR is set to 1. FRC should always be accessed in 16-bit
units; cannot be accessed in 8-bit units. FRC is initialized to H'0000.
10.2.2
Output Compare Registers A and B (OCRA and OCRB)
The FRT has two output compare registers, OCRA and OCRB, each of which is a 16-bit
readable/writable register whose contents are continually compared with the value in FRC. When
a match is detected (compare-match), the corresponding output compare flag (OCFA or OCFB) is
set to 1 in TCSR. OCR should always be accessed in 16-bit units; cannot be accessed in 8-bit
units. OCR is initialized to H'FFFF.
Section 10 16-Bit Free-Running Timer (FRT)
Rev. 1.00 Mar. 12, 2008 Page 375 of 1178
REJ09B0403-0100
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