Renesas H8S Family Hardware Manual page 554

Section 15 Serial Communication Interface with FIFO (SCIF)

Figure 15.1 shows a block diagram of the SCIF.

System clock

Receive shift register

Transmitter shift register

Receive buffer register

Transmitter holding register

FDLH, FDLL: Divisor latch H, L

Interrupt enable register

Interrupt identification register

Rev. 1.00 Mar. 12, 2008 Page 506 of 1178

REJ09B0403-0100

transmission/

SCIFCR: SCIF control register

Figure 15.1 Block Diagram of SCIF

Transmit FIFO

Transmission

Receive FIFO

Transfer clock

FIFO control register

Line control register

Modem control register

Line status register

Modem status register

Scratch pad register