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φ
Address bus
IOS (IOSE = 1)
CS256 (CS256E = 1)
AS (IOSE = 0)
*
RD
D15 to D8
Read
D7 to D0
HWR
LWR
Write
D15 to D8
D7 to D0
Note: * For external address space access, this signal is not output when the 256-Kbyte extended area
is accessed with CS256E = 1.
Figure 6.9 Bus Timing for 16-Bit, 2-State Access Space (Word Access)
Bus cycle
T
T
1
2
Valid
Valid
Rev. 1.00 Mar. 12, 2008 Page 133 of 1178
Section 6 Bus Controller (BSC)
Valid
Valid
REJ09B0403-0100
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