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Bit
Bit Name
1
IRIC
Initial
Value R/W
Description
2
0
R/(W)* I
C Bus Interface Interrupt Request Flag
Indicates that the I
request to the CPU.
IRIC is set at different times depending on the FS bit in
SAR and the WAIT bit in ICMR. See section 18.4.7, IRIC
Setting Timing and SCL Control. The conditions under
which IRIC is set also differ depending on the setting of the
ACKE bit in ICCR.
[Setting conditions]
2
I
C bus format master mode:
•
When a start condition is detected in the bus line state
after a start condition is issued (when the ICDRE flag is
set to 1 because of first frame transmission)
•
When a wait is inserted between the data and
acknowledge bit when the WAIT bit is 1 (fall of the 8th
transmit/receive clock)
•
At the end of data transfer (rise of the 9th
transmit/receive clock)
•
When a slave address is received after bus mastership
is lost
•
If 1 is received as the acknowledge bit (when the ACKB
bit in ICSR is set to 1) when the ACKE bit is 1
•
When the AL flag is set to 1 after bus mastership is lost
while the ALIE bit is 1
2
I
C bus format slave mode:
•
When the slave address (SVA or SVAX) matches
(when the AAS or AASX flag in ICSR is set to 1) and at
the end of data transfer up to the subsequent
retransmission start condition or stop condition
detection (rise of the 9th clock)
•
When the general call address is detected (when the 0
is received for R/W bit, and ADZ flag in ICSR is set to
1) and at the end of data reception up to the
subsequent retransmission start condition or stop
condition detection (rise of the 9th receive clock)
•
When 1 is received as an acknowledge bit while the
ACKE bit is 1 (when the ACKB bit is set to 1)
•
When a stop condition is detected while the STOPIM bit
is 0 (when the STOP or ESTP flag in ICSR is set to 1)
Section 18 I
2
C bus interface has issued an interrupt
Rev. 1.00 Mar. 12, 2008 Page 601 of 1178
2
C Bus Interface (IIC)
REJ09B0403-0100
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