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26.3 Register Descriptions....................................................................................................... 1022
26.3.1 Instruction Register (SDIR) ................................................................................ 1023
26.3.2 Bypass Register (SDBPR) .................................................................................. 1024
26.3.3 Boundary Scan Register (SDBSR) ..................................................................... 1024
26.3.4 ID Code Register (SDIDR)................................................................................. 1042
26.4 Operation ......................................................................................................................... 1043
26.4.1 TAP Controller State Transitions........................................................................ 1043
26.4.2 JTAG Reset......................................................................................................... 1044
26.5 Boundary Scan................................................................................................................. 1044
26.5.1 Supported Instructions ........................................................................................ 1044
26.6 Usage Notes ..................................................................................................................... 1047
Section 27 Clock Pulse Generator................................................................... 1051
27.1 Oscillator.......................................................................................................................... 1052
27.1.1 Connecting Crystal Resonator ............................................................................ 1052
27.1.2 External Clock Input Method ............................................................................. 1053
27.2 PLL Multiplier Circuit ..................................................................................................... 1054
27.3 Medium-Speed Clock Divider ......................................................................................... 1054
27.4 Bus Master Clock Select Circuit...................................................................................... 1054
27.5 Subclock Input Circuit ..................................................................................................... 1054
27.6 Subclock Waveform Shaping Circuit .............................................................................. 1054
27.7 Clock Select Circuit ......................................................................................................... 1055
27.8 Usage Notes ..................................................................................................................... 1056
27.8.1 Note on Resonator .............................................................................................. 1056
27.8.2 Notes on Board Design ....................................................................................... 1056
27.8.3 Note on Operation Check ................................................................................... 1056
Section 28 Power-Down Modes...................................................................... 1057
28.1 Register Descriptions....................................................................................................... 1058
28.1.1 Standby Control Register (SBYCR) ................................................................... 1058
28.1.2 Low-Power Control Register (LPWRCR) .......................................................... 1061
28.1.3 Module Stop Control Registers H, L, and A
(MSTPCRH, MSTPCRL, MSTPCRA) .............................................................. 1062
28.1.4 Sub-Chip Module Stop Control Registers BH, BL
(SUBMSTPBH, SUBMSTPBL)......................................................................... 1064
28.2 Mode Transitions and LSI States ..................................................................................... 1065
28.3 Medium-Speed Mode ...................................................................................................... 1067
28.4 Sleep Mode ...................................................................................................................... 1068
28.5 Software Standby Mode................................................................................................... 1069
28.6 Hardware Standby Mode ................................................................................................. 1071
Rev. 1.00 Mar. 12, 2008 Page xxvi of xIviii
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