Download Print this page

Renesas H8S Family Hardware Manual page 529

Advertisement

nth transfer frame
Ds
D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
TDRE
Transfer from TDR to TSR
TEND
FER/ERS
Figure 13.26 Data Re-transfer Operation in SCI Transmission Mode
Note that the TEND flag is set in different timings depending on the GM bit setting in SMR,
which is shown in figure 13.27.
I/O data
TXI
(TEND interrupt)
GM = 0
GM = 1
[Legend]
Ds:
Start bit
D0 to D7:
Data bits
Dp:
Parity bit
DE:
Error signal
etu:
Element Time Unit (time taken to transfer one bit)
Figure 13.27 TEND Flag Set Timings during Transmission
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Transfer from TDR to TSR
[2]
[1]
Ds
D0
D1
D2
D3
11.0 etu
Section 13 Serial Communication Interface (SCI)
Retransfer frame
(DE)
D4
D5
D6
D7
Dp
12.5 etu
Rev. 1.00 Mar. 12, 2008 Page 481 of 1178
(n + 1) th
transfer frame
Ds D0 D1 D2 D3 D4
Transfer from TDR to TSR
[3]
[3]
DE
Guard time
REJ09B0403-0100

Advertisement

loading

This manual is also suitable for:

R4f2472R4f2462H8s/2462H8s/2400 seriesH8s/2472