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15.3.14 SCIF Control Register (SCIFCR) ......................................................................... 524
15.4 Operation ........................................................................................................................... 526
15.4.1 Baud Rate ............................................................................................................. 526
15.4.2 Operation in Asynchronous Communication........................................................ 527
15.4.3 Initialization of the SCIF ...................................................................................... 528
15.4.4 Data Transmission/Reception with Flow Control................................................. 531
15.4.5 Data Transmission/Reception Through the LPC Interface ................................... 537
15.5 Interrupt Sources................................................................................................................ 539
15.6 Usage Note......................................................................................................................... 539
15.6.1 Power-Down Mode When LCLK is Selected for SCLK ...................................... 539
Section 16 Serial Pin Multiplexed Modes ......................................................... 541
16.1 Features.............................................................................................................................. 541
16.2 Input/Output Pins............................................................................................................... 542
16.3 Register Descriptions......................................................................................................... 543
16.3.1 Serial Multiplexed Mode Register 0 (SMR0) ....................................................... 543
16.3.2 Serial Multiplexed Mode Register 1 (SMR1) ....................................................... 544
16.4 Operation of Serial Pin Multiplexed Modes ...................................................................... 545
(Default; SMR0 Register [bits SM2, SM1, SM0] = [0 0 0])................................. 545
(SMR0 Register [bits SM2, SM1, SM0] = [0 0 1])............................................... 546
(SMR0 Register [bits SM2, SM1, SM0] = [0 1 0])............................................... 547
16.4.4 Serial Pin Multiplexed Mode 3
(SMR0 Register [bits SM2, SM1, SM0] = [0 1 1])............................................... 548
16.4.5 Serial Pin Multiplexed Mode 4
(SMR0 Register [bits SM2, SM1, SM0] = [1 0 0])............................................... 549
16.5 Serial Port Pin Configuration............................................................................................. 550
Section 17 Synchronous Serial Communication Unit (Ssu) ............................ 551
17.1 Features.............................................................................................................................. 551
17.2 Input/Output Pins............................................................................................................... 553
17.3 Register Descriptions......................................................................................................... 553
17.3.1 SS Control Register H (SSCRH) .......................................................................... 554
17.3.2 SS Control Register L (SSCRL) ........................................................................... 556
17.3.3 SS Mode Register (SSMR) ................................................................................... 557
17.3.4 SS Enable Register (SSER) .................................................................................. 558
17.3.5 SS Status Register (SSSR).................................................................................... 559
17.3.6 SS Control Register 2 (SSCR2) ............................................................................ 561
Rev. 1.00 Mar. 12, 2008 Page xviii of xIviii
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